?? reg32b.rpt
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Project Information c:\maxplus2\1502d\test11\reg32b.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 06/17/2002 13:50:53
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
REG32B
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
reg32b EPM7128SQC100-6 33 32 0 32 0 25 %
User Pins: 33 32 0
Project Information c:\maxplus2\1502d\test11\reg32b.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'load' chosen for auto global Clock
Device-Specific Information: c:\maxplus2\1502d\test11\reg32b.rpt
reg32b
***** Logic for device 'reg32b' compiled without errors.
Device: EPM7128SQC100-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
V
d d d d d d C d d d V d d d
i i i i i i C l o o o C o o o
n n n G n n n I G G G o G u u u C u u u
2 2 2 N 2 2 2 N N N N a N t t t I t t t
0 5 6 D 7 8 9 T D D D d D 7 0 1 O 6 2 4
------------------------------------------_
/ 100 98 96 94 92 90 88 86 84 82 |_
/ 99 97 95 93 91 89 87 85 83 81 |
din21 | 1 80 | dout8
din22 | 2 79 | dout3
din23 | 3 78 | dout5
din24 | 4 77 | dout9
VCCIO | 5 76 | GND
#TDI | 6 75 | #TDO
din4 | 7 74 | dout11
din5 | 8 73 | dout10
din18 | 9 72 | dout13
din19 | 10 71 | dout12
din0 | 11 70 | dout14
din31 | 12 69 | dout15
GND | 13 68 | VCCIO
din10 | 14 67 | dout16
din30 | 15 66 | dout17
din9 | 16 EPM7128SQC100-6 65 | dout18
#TMS | 17 64 | #TCK
din13 | 18 63 | dout23
din14 | 19 62 | dout24
VCCIO | 20 61 | GND
din15 | 21 60 | dout25
din6 | 22 59 | dout26
din16 | 23 58 | dout27
din1 | 24 57 | dout22
din17 | 25 56 | dout21
din2 | 26 55 | dout20
din3 | 27 54 | dout19
GND | 28 53 | VCCIO
din8 | 29 52 | RESERVED
RESERVED | 30 51 | RESERVED
| 32 34 36 38 40 42 44 46 48 50 _|
\ 31 33 35 37 39 41 43 45 47 49 |
\-------------------------------------------
R R R d R V d R d G V d d d G d R R R R
E E E i E C i E i N C o o o N o E E E E
S S S n S C n S n D C u u u D u S S S S
E E E 1 E I 1 E 7 I t t t t E E E E
R R R 1 R O 2 R N 3 3 2 2 R R R R
V V V V V T 1 0 9 8 V V V V
E E E E E E E E E
D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\maxplus2\1502d\test11\reg32b.rpt
reg32b
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 10/10(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 10/10(100%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 0/16( 0%) 10/10(100%) 0/16( 0%) 0/36( 0%)
D: LC49 - LC64 0/16( 0%) 4/10( 40%) 0/16( 0%) 0/36( 0%)
E: LC65 - LC80 4/16( 25%) 4/10( 40%) 0/16( 0%) 4/36( 11%)
F: LC81 - LC96 9/16( 56%) 10/10(100%) 0/16( 0%) 9/36( 25%)
G: LC97 - LC112 9/16( 56%) 10/10(100%) 0/16( 0%) 9/36( 25%)
H: LC113 - LC128 10/16( 62%) 10/10(100%) 0/16( 0%) 10/36( 27%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 68/80 ( 85%)
Total logic cells used: 32/128 ( 25%)
Total shareable expanders used: 0/128 ( 0%)
Total Turbo logic cells used: 32/128 ( 25%)
Total shareable expanders not available (n/a): 0/128 ( 0%)
Average fan-in: 2.00
Total fan-in: 64
Total input pins required: 33
Total fast input logic cells required: 0
Total output pins required: 32
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 32
Total flipflops required: 32
Total product terms required: 32
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 128 ( 0%)
Device-Specific Information: c:\maxplus2\1502d\test11\reg32b.rpt
reg32b
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
11 (24) (B) INPUT 0 0 0 0 0 1 0 din0
24 (38) (C) INPUT 0 0 0 0 0 1 0 din1
26 (35) (C) INPUT 0 0 0 0 0 1 0 din2
27 (33) (C) INPUT 0 0 0 0 0 1 0 din3
7 (30) (B) INPUT 0 0 0 0 0 1 0 din4
8 (29) (B) INPUT 0 0 0 0 0 1 0 din5
22 (41) (C) INPUT 0 0 0 0 0 1 0 din6
39 (49) (D) INPUT 0 0 0 0 0 1 0 din7
29 (64) (D) INPUT 0 0 0 0 0 1 0 din8
16 (17) (B) INPUT 0 0 0 0 0 1 0 din9
14 (21) (B) INPUT 0 0 0 0 0 1 0 din10
34 (56) (D) INPUT 0 0 0 0 0 1 0 din11
37 (53) (D) INPUT 0 0 0 0 0 1 0 din12
18 (46) (C) INPUT 0 0 0 0 0 1 0 din13
19 (45) (C) INPUT 0 0 0 0 0 1 0 din14
21 (43) (C) INPUT 0 0 0 0 0 1 0 din15
23 (40) (C) INPUT 0 0 0 0 0 1 0 din16
25 (37) (C) INPUT 0 0 0 0 0 1 0 din17
9 (27) (B) INPUT 0 0 0 0 0 1 0 din18
10 (25) (B) INPUT 0 0 0 0 0 1 0 din19
100 (8) (A) INPUT 0 0 0 0 0 1 0 din20
1 (6) (A) INPUT 0 0 0 0 0 1 0 din21
2 (5) (A) INPUT 0 0 0 0 0 1 0 din22
3 (3) (A) INPUT 0 0 0 0 0 1 0 din23
4 (1) (A) INPUT 0 0 0 0 0 1 0 din24
99 (9) (A) INPUT 0 0 0 0 0 1 0 din25
98 (11) (A) INPUT 0 0 0 0 0 1 0 din26
96 (13) (A) INPUT 0 0 0 0 0 1 0 din27
95 (14) (A) INPUT 0 0 0 0 0 1 0 din28
94 (16) (A) INPUT 0 0 0 0 0 1 0 din29
15 (19) (B) INPUT 0 0 0 0 0 1 0 din30
12 (22) (B) INPUT 0 0 0 0 0 1 0 din31
89 - - INPUT G 0 0 0 0 0 0 0 load
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\maxplus2\1502d\test11\reg32b.rpt
reg32b
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
86 126 H FF + t 0 0 0 1 0 0 0 dout0
85 125 H FF + t 0 0 0 1 0 0 0 dout1
82 121 H FF + t 0 0 0 1 0 0 0 dout2
79 117 H FF + t 0 0 0 1 0 0 0 dout3
81 120 H FF + t 0 0 0 1 0 0 0 dout4
78 115 H FF + t 0 0 0 1 0 0 0 dout5
83 123 H FF + t 0 0 0 1 0 0 0 dout6
87 128 H FF + t 0 0 0 1 0 0 0 dout7
80 118 H FF + t 0 0 0 1 0 0 0 dout8
77 113 H FF + t 0 0 0 1 0 0 0 dout9
73 109 G FF + t 0 0 0 1 0 0 0 dout10
74 110 G FF + t 0 0 0 1 0 0 0 dout11
71 105 G FF + t 0 0 0 1 0 0 0 dout12
72 107 G FF + t 0 0 0 1 0 0 0 dout13
70 104 G FF + t 0 0 0 1 0 0 0 dout14
69 102 G FF + t 0 0 0 1 0 0 0 dout15
67 101 G FF + t 0 0 0 1 0 0 0 dout16
66 99 G FF + t 0 0 0 1 0 0 0 dout17
65 97 G FF + t 0 0 0 1 0 0 0 dout18
54 81 F FF + t 0 0 0 1 0 0 0 dout19
55 83 F FF + t 0 0 0 1 0 0 0 dout20
56 85 F FF + t 0 0 0 1 0 0 0 dout21
57 86 F FF + t 0 0 0 1 0 0 0 dout22
63 94 F FF + t 0 0 0 1 0 0 0 dout23
62 93 F FF + t 0 0 0 1 0 0 0 dout24
60 91 F FF + t 0 0 0 1 0 0 0 dout25
59 89 F FF + t 0 0 0 1 0 0 0 dout26
58 88 F FF + t 0 0 0 1 0 0 0 dout27
46 70 E FF + t 0 0 0 1 0 0 0 dout28
44 69 E FF + t 0 0 0 1 0 0 0 dout29
43 67 E FF + t 0 0 0 1 0 0 0 dout30
42 65 E FF + t 0 0 0 1 0 0 0 dout31
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\maxplus2\1502d\test11\reg32b.rpt
reg32b
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+------- LC70 dout28
| +----- LC69 dout29
| | +--- LC67 dout30
| | | +- LC65 dout31
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'E'
LC | | | | | A B C D E F G H | Logic cells that feed LAB 'E':
Pin
95 -> * - - - | - - - - * - - - | <-- din28
94 -> - * - - | - - - - * - - - | <-- din29
15 -> - - * - | - - - - * - - - | <-- din30
12 -> - - - * | - - - - * - - - | <-- din31
89 -> - - - - | - - - - - - - - | <-- load
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\maxplus2\1502d\test11\reg32b.rpt
reg32b
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+----------------- LC81 dout19
| +--------------- LC83 dout20
| | +------------- LC85 dout21
| | | +----------- LC86 dout22
| | | | +--------- LC94 dout23
| | | | | +------- LC93 dout24
| | | | | | +----- LC91 dout25
| | | | | | | +--- LC89 dout26
| | | | | | | | +- LC88 dout27
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'F'
LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
Pin
10 -> * - - - - - - - - | - - - - - * - - | <-- din19
100 -> - * - - - - - - - | - - - - - * - - | <-- din20
1 -> - - * - - - - - - | - - - - - * - - | <-- din21
2 -> - - - * - - - - - | - - - - - * - - | <-- din22
3 -> - - - - * - - - - | - - - - - * - - | <-- din23
4 -> - - - - - * - - - | - - - - - * - - | <-- din24
99 -> - - - - - - * - - | - - - - - * - - | <-- din25
98 -> - - - - - - - * - | - - - - - * - - | <-- din26
96 -> - - - - - - - - * | - - - - - * - - | <-- din27
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