package n_bit_int is 
subtype word26 is integer range 0 to 2**26-1;
end n_bit_int;

LIBRARY work;
USE work.n_bit_int.all;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;


ENTITY cic3r IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
	(
		clk : IN STD_LOGIC;
		xin : IN STD_LOGIC_vector(7 downto 0);
		yout : OUT STD_LOGIC_vector(8 downto 0));
END cic3r;

ARCHITECTURE flex OF cic3r IS
	type state_type is (hold,sample);
	signal state:state_type;
	signal count:integer range 0 to 31;
	signal clk2:std_logic;
	signal x:std_logic_vector(7 downto 0);
	signal sxtx:std_logic_vector(25 downto 0);
	signal i0,i1,i2:word26;
	signal i2d1,i2d2,i2d3,i2d4,c1,c0:word26;
	signal c1d1,c1d2,c1d3,c1d4,c2:word26;
	signal c2d1,c2d2,c2d3,c2d4,c3:word26;
BEGIN
process
begin 
   wait until clk='0';
   case state is 
    when hold=>if count<31 then
                  state<=hold;
                else
                  state<=sample;
                end if;
    when others=>state<=hold;
    end case;
 end process;
sxt: process(x)
    begin
         sxtx(7 downto 0)<=x;
         for k in 25 downto 8 loop
         sxtx(k)<=x(x'high);
         end loop;
   end process sxt;

int:process
begin 
  wait until clk='1';
  x<=xin;
  i0<=i0+conv_integer(sxtx);
  i1<=i1+i0;
  i2<=i2+i1;
case state is 
    when sample=>
     c0<=i2;
     count<=0;
    when others=>
     count<=count+1;
end case;
if(count>8)and(count<16)then
   clk2<='1';
 else
   clk2<='0';
 end if ;
end process int;

comb:process
begin
  wait until clk2='1';
  i2d1<=c0;
  i2d2<=i2d1;
  c1<=c0-i2d2;
  c1d1<=c1;
  c1d2<=c1d1;
  c2<=c1-c1d2;
  c2d1<=c2;
  c2d2<=c2d1;
  c3<=c2-c2d2;
end process comb;
yout<=conv_std_logic_vector(c3/2**17,9);
END flex;