Release 8.1i - xst I.24Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to ./xst/projnav.tmpCPU : 0.00 / 0.89 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.89 s | Elapsed : 0.00 / 1.00 s --> Reading design: lcd_top.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis     4.1) HDL Synthesis Report  5) Advanced HDL Synthesis     5.1) Advanced HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "lcd_top.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "lcd_top"Output Format                      : NGCTarget Device                      : xc3s400-4-pq208---- Source OptionsTop Module Name                    : lcd_topAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESROM Style                          : AutoMux Extraction                     : YESResource Sharing                   : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 8Register Duplication               : YESSlice Packing                      : YESPack IO Registers into IOBs        : autoEquivalent register Removal        : YES---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NORTL Output                         : YesGlobal Optimization                : AllClockNetsWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : lcd_top.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yes==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "D:/Xilinx/disk1/medule/lcd.v" in library workCompiling verilog file "lcd_top.v" in library workModule <lcd> compiledModule <lcd_top> compiledNo errors in compilationAnalysis of file <"lcd_top.prj"> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <lcd_top>.Module <lcd_top> is correct for synthesis. Analyzing module <lcd>.	s0 = 32'sb00000000000000000000000000000000	s1 = 32'sb00000000000000000000000000000001	s2 = 32'sb00000000000000000000000000000010	s3 = 32'sb00000000000000000000000000000011	s4 = 32'sb00000000000000000000000000000100	s5 = 32'sb00000000000000000000000000000101	s6 = 32'sb00000000000000000000000000000110	s7 = 32'sb00000000000000000000000000000111	s8 = 32'sb00000000000000000000000000001000	s9 = 32'sb00000000000000000000000000001001	s10 = 32'sb00000000000000000000000000001010	s11 = 32'sb00000000000000000000000000001011	s12 = 32'sb00000000000000000000000000001100	s13 = 32'sb00000000000000000000000000001101	s14 = 32'sb00000000000000000000000000001110	s15 = 32'sb00000000000000000000000000001111Module <lcd> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================INFO:Xst:1304 - Contents of register <num> in unit <lcd_top> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <RW> in unit <lcd> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <DelayT> in unit <lcd> never changes during circuit operation. The register is replaced by logic.Synthesizing Unit <lcd>.    Related source file is "D:/Xilinx/disk1/medule/lcd.v".WARNING:Xst:1780 - Signal <char_dir> is never used or assigned.    Found 8-bit register for signal <DDout>.    Found 1-bit register for signal <E>.    Found 1-bit register for signal <RS>.    Found 33-bit comparator less for signal <$n0008> created at line 72.    Found 32-bit up counter for signal <i>.    Found 1-bit register for signal <start>.    Found 4-bit register for signal <state>.    Found 4-bit register for signal <zstate>.    Summary:	inferred   1 Counter(s).	inferred  19 D-type flip-flop(s).	inferred   1 Comparator(s).Unit <lcd> synthesized.Synthesizing Unit <lcd_top>.    Related source file is "lcd_top.v".WARNING:Xst:646 - Signal <num10> is assigned but never used.WARNING:Xst:646 - Signal <num1> is assigned but never used.    Found 23-bit up counter for signal <display_cnt>.    Found 8-bit register for signal <display_dir>.    Found 1-bit register for signal <display_start>.    Summary:	inferred   1 Counter(s).	inferred   1 D-type flip-flop(s).Unit <lcd_top> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Counters                                             : 2 23-bit up counter                                     : 1 32-bit up counter                                     : 1# Registers                                            : 8 1-bit register                                        : 4 4-bit register                                        : 2 8-bit register                                        : 2# Comparators                                          : 1 33-bit comparator less                                : 1==================================================================================================================================================*                       Advanced HDL Synthesis                          *==================================================================================================================================================Advanced HDL Synthesis ReportMacro Statistics# Counters                                             : 2 23-bit up counter                                     : 1 32-bit up counter                                     : 1# Registers                                            : 28 Flip-Flops                                            : 28# Comparators                                          : 1 33-bit comparator less                                : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================WARNING:Xst:1710 - FF/Latch  <display_dir_4> (without init value) has a constant value of 0 in block <lcd_top>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <display_dir_5> (without init value) has a constant value of 0 in block <lcd_top>.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <display_dir_6> (without init value) has a constant value of 0 in block <lcd_top>.Loading device for application Rf_Device from file '3s400.nph' in environment D:\Xilinx.