?? sramcontroller.rpt
字號:
48 - - - 15 OUTPUT 0 1 0 0 address7
72 - - A -- OUTPUT 0 1 0 0 address8
51 - - - 18 OUTPUT 0 1 0 0 address9
50 - - - 17 OUTPUT 0 1 0 0 address10
19 - - A -- OUTPUT 0 1 0 0 ce
21 - - B -- OUTPUT 0 1 0 0 dataout0
80 - - - 23 OUTPUT 0 1 0 0 dataout1
47 - - - 14 OUTPUT 0 1 0 0 dataout2
66 - - B -- OUTPUT 0 1 0 0 dataout3
79 - - - 24 OUTPUT 0 1 0 0 dataout4
83 - - - 13 OUTPUT 0 1 0 0 dataout5
78 - - - 24 OUTPUT 0 1 0 0 dataout6
69 - - A -- OUTPUT 0 1 0 0 dataout7
59 - - C -- OUTPUT 0 1 0 0 memdataout0
58 - - C -- OUTPUT 0 1 0 0 memdataout1
52 - - - 19 OUTPUT 0 1 0 0 memdataout2
53 - - - 20 OUTPUT 0 1 0 0 memdataout3
61 - - C -- OUTPUT 0 1 0 0 memdataout4
60 - - C -- OUTPUT 0 1 0 0 memdataout5
24 - - B -- OUTPUT 0 1 0 0 memdataout6
25 - - B -- OUTPUT 0 1 0 0 memdataout7
65 - - B -- OUTPUT 0 1 0 0 oe
30 - - C -- OUTPUT 0 1 0 0 we
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\my documents\my_vhdl\sram_controller\sramcontroller.rpt
sramcontroller
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 22 AND2 0 2 0 3 |LPM_ADD_SUB:613|addcore:adder|:87
- 4 - A 22 AND2 0 2 0 3 |LPM_ADD_SUB:613|addcore:adder|:91
- 2 - A 20 AND2 0 2 0 3 |LPM_ADD_SUB:613|addcore:adder|:95
- 3 - A 20 AND2 0 2 0 3 |LPM_ADD_SUB:613|addcore:adder|:99
- 7 - A 20 AND2 0 2 0 3 |LPM_ADD_SUB:613|addcore:adder|:103
- 2 - A 15 AND2 0 2 0 3 |LPM_ADD_SUB:613|addcore:adder|:107
- 4 - A 15 AND2 0 2 0 3 |LPM_ADD_SUB:613|addcore:adder|:111
- 2 - A 18 AND2 0 2 0 3 |LPM_ADD_SUB:613|addcore:adder|:115
- 1 - A 18 AND2 0 2 0 5 |LPM_ADD_SUB:613|addcore:adder|:119
- 7 - C 20 DFFE + 1 2 1 0 :18
- 5 - C 20 DFFE + 1 2 1 0 :20
- 4 - C 20 DFFE + 1 2 1 0 :22
- 3 - C 20 DFFE + 1 2 1 0 :24
- 2 - C 20 DFFE + 1 2 1 0 :26
- 1 - C 20 DFFE + 1 2 1 0 :28
- 6 - C 20 DFFE + 1 2 1 0 :30
- 8 - C 20 DFFE + 1 2 1 0 :32
- 7 - A 24 DFFE + 1 2 1 0 :34
- 4 - A 24 DFFE + 1 2 1 0 :36
- 2 - A 13 DFFE + 1 2 1 0 :38
- 8 - A 24 DFFE + 1 2 1 0 :40
- 2 - A 24 DFFE + 1 2 1 0 :42
- 4 - A 13 DFFE + 1 2 1 0 :44
- 3 - A 24 DFFE + 1 2 1 0 :46
- 1 - A 24 DFFE + 1 2 1 0 :48
- 3 - A 18 DFFE + 0 3 1 3 :50
- 4 - A 18 DFFE + 0 3 1 1 :52
- 3 - A 15 DFFE + 0 3 1 1 :54
- 1 - A 15 DFFE + 0 3 1 1 :56
- 6 - A 15 DFFE + 0 3 1 1 :58
- 1 - A 20 DFFE + 0 3 1 1 :60
- 4 - A 20 DFFE + 0 3 1 1 :62
- 5 - A 20 DFFE + 0 3 1 1 :64
- 3 - A 22 DFFE + 0 3 1 1 :66
- 6 - A 22 DFFE + 0 3 1 1 :68
- 7 - A 22 DFFE + 0 1 1 3 :70
- 7 - A 19 DFFE + 0 3 1 0 :72
- 4 - A 14 DFFE + 0 3 0 8 counter3 (:76)
- 1 - A 14 DFFE + 0 2 0 9 counter2 (:77)
- 2 - A 14 DFFE + 0 3 0 8 counter1 (:78)
- 1 - A 23 DFFE + 0 0 0 9 counter0 (:79)
- 5 - A 24 DFFE +s 0 3 1 0 read~1 (~80~1)
- 6 - A 24 DFFE + 0 3 1 16 read (:80)
- 1 - A 13 OR2 s 0 2 0 1 ~267~1
- 8 - A 13 AND2 s 0 2 0 10 ~267~2
- 6 - A 14 AND2 0 4 0 9 :267
- 7 - A 14 AND2 s 0 4 0 1 ~276~1
- 5 - A 14 OR2 ! 0 4 0 1 :276
- 6 - A 18 AND2 0 4 0 2 :303
- 5 - A 18 OR2 s 0 3 0 10 ~747~1
- 8 - A 18 OR2 s 0 3 0 1 ~770~1
- 7 - A 18 OR2 s 0 3 0 1 ~788~1
- 8 - A 15 OR2 s 0 3 0 1 ~806~1
- 7 - A 15 OR2 s 0 3 0 1 ~824~1
- 5 - A 15 OR2 s 0 3 0 1 ~842~1
- 8 - A 20 OR2 s 0 3 0 1 ~860~1
- 6 - A 20 OR2 s 0 3 0 1 ~878~1
- 5 - A 22 OR2 s 0 3 0 1 ~896~1
- 8 - A 22 OR2 s 0 3 0 1 ~914~1
- 2 - A 22 OR2 s 0 3 0 1 ~932~1
- 3 - A 14 AND2 s ! 0 4 0 13 ~950~1
- 8 - A 14 AND2 s ! 0 4 0 8 ~1112~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\my documents\my_vhdl\sram_controller\sramcontroller.rpt
sramcontroller
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 0/ 48( 0%) 20/ 48( 41%) 3/16( 18%) 5/16( 31%) 0/16( 0%)
B: 3/ 96( 3%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
C: 10/ 96( 10%) 0/ 48( 0%) 4/ 48( 8%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\my documents\my_vhdl\sram_controller\sramcontroller.rpt
sramcontroller
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 34 clock
Device-Specific Information:e:\my documents\my_vhdl\sram_controller\sramcontroller.rpt
sramcontroller
** EQUATIONS **
clock : INPUT;
datain0 : INPUT;
datain1 : INPUT;
datain2 : INPUT;
datain3 : INPUT;
datain4 : INPUT;
datain5 : INPUT;
datain6 : INPUT;
datain7 : INPUT;
memdatain0 : INPUT;
memdatain1 : INPUT;
memdatain2 : INPUT;
memdatain3 : INPUT;
memdatain4 : INPUT;
memdatain5 : INPUT;
memdatain6 : INPUT;
memdatain7 : INPUT;
-- Node name is 'address0'
-- Equation name is 'address0', type is output
address0 = _LC7_A22;
-- Node name is 'address1'
-- Equation name is 'address1', type is output
address1 = _LC6_A22;
-- Node name is 'address2'
-- Equation name is 'address2', type is output
address2 = _LC3_A22;
-- Node name is 'address3'
-- Equation name is 'address3', type is output
address3 = _LC5_A20;
-- Node name is 'address4'
-- Equation name is 'address4', type is output
address4 = _LC4_A20;
-- Node name is 'address5'
-- Equation name is 'address5', type is output
address5 = _LC1_A20;
-- Node name is 'address6'
-- Equation name is 'address6', type is output
address6 = _LC6_A15;
-- Node name is 'address7'
-- Equation name is 'address7', type is output
address7 = _LC1_A15;
-- Node name is 'address8'
-- Equation name is 'address8', type is output
address8 = _LC3_A15;
-- Node name is 'address9'
-- Equation name is 'address9', type is output
address9 = _LC4_A18;
-- Node name is 'address10'
-- Equation name is 'address10', type is output
address10 = _LC3_A18;
-- Node name is 'ce'
-- Equation name is 'ce', type is output
ce = _LC7_A19;
-- Node name is ':79' = 'counter0'
-- Equation name is 'counter0', location is LC1_A23, type is buried.
counter0 = DFFE(!counter0, GLOBAL( clock), VCC, VCC, VCC);
-- Node name is ':78' = 'counter1'
-- Equation name is 'counter1', location is LC2_A14, type is buried.
counter1 = DFFE( _EQ001, GLOBAL( clock), VCC, VCC, VCC);
_EQ001 = !counter0 & counter1
# counter0 & !counter1 & !counter3
# counter0 & !counter1 & counter2;
-- Node name is ':77' = 'counter2'
-- Equation name is 'counter2', location is LC1_A14, type is buried.
counter2 = DFFE( _EQ002, GLOBAL( clock), VCC, VCC, VCC);
_EQ002 = !counter1 & counter2
# !counter0 & counter2
# counter0 & counter1 & !counter2;
-- Node name is ':76' = 'counter3'
-- Equation name is 'counter3', location is LC4_A14, type is buried.
counter3 = DFFE( _EQ003, GLOBAL( clock), VCC, VCC, VCC);
_EQ003 = !counter0 & counter3
# counter0 & counter1 & counter2 & !counter3
# counter1 & !counter2 & counter3
# !counter1 & counter2 & counter3;
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