Project Information                                          e:\vhdcx\qpsk.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 10/30/2008 10:18:36

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

qpsk      EPM7128SLC84-15  1        11       0      85      65          66 %

User Pins:                 1        11       0  



Project Information                                          e:\vhdcx\qpsk.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Primitive 'CS' is stuck at GND


Project Information                                          e:\vhdcx\qpsk.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'CP' chosen for auto global Clock


Project Information                                          e:\vhdcx\qpsk.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

qpsk@58                           CD
qpsk@83                           CP
qpsk@79                           CS
qpsk@60                           CW
qpsk@75                           N0
qpsk@74                           N1
qpsk@70                           N2
qpsk@69                           N3
qpsk@68                           N4
qpsk@64                           N5
qpsk@65                           N6
qpsk@61                           N7


Project Information                                          e:\vhdcx\qpsk.rpt

** FILE HIERARCHY **



|add1:1|
|add1:1|lpm_add_sub:56|
|add1:1|lpm_add_sub:56|addcore:adder|
|add1:1|lpm_add_sub:56|addcore:adder|addcore:adder1|
|add1:1|lpm_add_sub:56|addcore:adder|addcore:adder0|
|add1:1|lpm_add_sub:56|altshift:result_ext_latency_ffs|
|add1:1|lpm_add_sub:56|altshift:carry_ext_latency_ffs|
|add1:1|lpm_add_sub:56|altshift:oflow_ext_latency_ffs|
|cun1:2|
|pz:4|
|pz:4|lpm_add_sub:168|
|pz:4|lpm_add_sub:168|addcore:adder|
|pz:4|lpm_add_sub:168|addcore:adder|addcore:adder0|
|pz:4|lpm_add_sub:168|altshift:result_ext_latency_ffs|
|pz:4|lpm_add_sub:168|altshift:carry_ext_latency_ffs|
|pz:4|lpm_add_sub:168|altshift:oflow_ext_latency_ffs|
|pz:4|lpm_add_sub:238|
|pz:4|lpm_add_sub:238|addcore:adder|
|pz:4|lpm_add_sub:238|addcore:adder|addcore:adder1|
|pz:4|lpm_add_sub:238|addcore:adder|addcore:adder0|
|pz:4|lpm_add_sub:238|altshift:result_ext_latency_ffs|
|pz:4|lpm_add_sub:238|altshift:carry_ext_latency_ffs|
|pz:4|lpm_add_sub:238|altshift:oflow_ext_latency_ffs|
|suocunf:5|
|fp2:17|
|fp2:17|lpm_add_sub:192|
|fp2:17|lpm_add_sub:192|addcore:adder|
|fp2:17|lpm_add_sub:192|addcore:adder|addcore:adder1|
|fp2:17|lpm_add_sub:192|addcore:adder|addcore:adder0|
|fp2:17|lpm_add_sub:192|altshift:result_ext_latency_ffs|
|fp2:17|lpm_add_sub:192|altshift:carry_ext_latency_ffs|
|fp2:17|lpm_add_sub:192|altshift:oflow_ext_latency_ffs|
|fp2:17|lpm_add_sub:219|
|fp2:17|lpm_add_sub:219|addcore:adder|
|fp2:17|lpm_add_sub:219|addcore:adder|addcore:adder1|
|fp2:17|lpm_add_sub:219|addcore:adder|addcore:adder0|
|fp2:17|lpm_add_sub:219|altshift:result_ext_latency_ffs|
|fp2:17|lpm_add_sub:219|altshift:carry_ext_latency_ffs|
|fp2:17|lpm_add_sub:219|altshift:oflow_ext_latency_ffs|


Device-Specific Information:                                 e:\vhdcx\qpsk.rpt
qpsk

***** Logic for device 'qpsk' compiled without errors.




Device: EPM7128SLC84-15

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff
    MultiVolt I/O                              = OFF

              R  R  R  R     R  R  R                    R  R        R  R     
              E  E  E  E     E  E  E                    E  E        E  E     
              S  S  S  S     S  S  S  V                 S  S        S  S     
              E  E  E  E     E  E  E  C                 E  E     V  E  E     
              R  R  R  R     R  R  R  C                 R  R     C  R  R     
              V  V  V  V  G  V  V  V  I  G  G  G     G  V  V     C  V  V     
              E  E  E  E  N  E  E  E  N  N  N  N  C  N  E  E  C  I  E  E  N  
              D  D  D  D  D  D  D  D  T  D  D  D  P  D  D  D  S  O  D  D  0  
            -----------------------------------------------------------------_ 
          /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
RESERVED | 12                                                              74 | N1 
   VCCIO | 13                                                              73 | RESERVED 
    #TDI | 14                                                              72 | GND 
RESERVED | 15                                                              71 | #TDO 
RESERVED | 16                                                              70 | N2 
RESERVED | 17                                                              69 | N3 
RESERVED | 18                                                              68 | N4 
     GND | 19                                                              67 | RESERVED 
RESERVED | 20                                                              66 | VCCIO 
RESERVED | 21                                                              65 | N6 
RESERVED | 22                       EPM7128SLC84-15                        64 | N5 
    #TMS | 23                                                              63 | RESERVED 
RESERVED | 24                                                              62 | #TCK 
RESERVED | 25                                                              61 | N7 
   VCCIO | 26                                                              60 | CW 
RESERVED | 27                                                              59 | GND 
RESERVED | 28                                                              58 | CD 
RESERVED | 29                                                              57 | RESERVED 
RESERVED | 30                                                              56 | RESERVED 
RESERVED | 31                                                              55 | RESERVED 
     GND | 32                                                              54 | RESERVED 
         |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
           ------------------------------------------------------------------ 
              R  R  R  R  R  V  R  R  R  G  V  R  R  R  G  R  R  R  R  R  V  
              E  E  E  E  E  C  E  E  E  N  C  E  E  E  N  E  E  E  E  E  C  
              S  S  S  S  S  C  S  S  S  D  C  S  S  S  D  S  S  S  S  S  C  
              E  E  E  E  E  I  E  E  E     I  E  E  E     E  E  E  E  E  I  
              R  R  R  R  R  O  R  R  R     N  R  R  R     R  R  R  R  R  O  
              V  V  V  V  V     V  V  V     T  V  V  V     V  V  V  V  V     
              E  E  E  E  E     E  E  E        E  E  E     E  E  E  E  E     
              D  D  D  D  D     D  D  D        D  D  D     D  D  D  D  D     


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:                                 e:\vhdcx\qpsk.rpt
qpsk

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     1/16(  6%)   0/ 8(  0%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32     0/16(  0%)   1/ 8( 12%)   0/16(  0%)   0/36(  0%) 
C:    LC33 - LC48    15/16( 93%)   1/ 8( 12%)  11/16( 68%)  22/36( 61%) 
D:    LC49 - LC64    16/16(100%)   0/ 8(  0%)   0/16(  0%)  21/36( 58%) 
E:    LC65 - LC80    16/16(100%)   0/ 8(  0%)  13/16( 81%)  23/36( 63%) 
F:    LC81 - LC96    16/16(100%)   4/ 8( 50%)  16/16(100%)  30/36( 83%) 
G:   LC97 - LC112     5/16( 31%)   6/ 8( 75%)  13/16( 81%)  10/36( 27%) 
H:  LC113 - LC128    16/16(100%)   3/ 8( 37%)  13/16( 81%)  17/36( 47%) 


Total dedicated input pins used:                 1/4      ( 25%)
Total I/O pins used:                            15/64     ( 23%)
Total logic cells used:                         85/128    ( 66%)
Total shareable expanders used:                 65/128    ( 50%)
Total Turbo logic cells used:                   85/128    ( 66%)
Total shareable expanders not available (n/a):   1/128    (  0%)
Average fan-in:                                  7.32
Total fan-in:                                   623