?? uart.vhd.txt
字號:
-------------------------------
--uart send & recive for FPGA
-- 2009
-------------------------------
LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY uart is
PORT(clk: IN STD_LOGIC;
rx : IN STD_LOGIC;
LED: OUT STD_LOGIC_VECTOR(7 downto 0);
tx,outp : OUT STD_LOGIC
);
END uart;
ARCHITECTURE BEHAVIOR OF uart IS
SIGNAL buf2 : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL START_BIT :STD_LOGIC;
SIGNAL clk_2,clk_3 : STD_LOGIC;
SIGNAL recive_clk_enable :STD_LOGIC;
-------------------------------------------------------------------------------
FUNCTION parity_generator(input_vector: STD_LOGIC_VECTOR) return std_logic is
variable temp : STD_LOGIC;
BEGIN
temp:='0';
for i in input_vector'range loop
temp:=temp xor input_vector(i);
end loop;
return temp;
END parity_generator;
BEGIN
SEND: BLOCK--------------------------------------- S E N D ----------------------------------------------
SIGNAL Transmit_buf : STD_LOGIC_VECTOR(15 downto 0);
BEGIN
PROCESS(clk) is
VARIABLE cnt :INTEGER RANGE 0 TO 1706;
BEGIN
IF RISING_EDGE(clk) THEN
cnt:=cnt+1;
IF cnt<854 THEN
clk_2<='0';
ELSIF cnt<1707 and cnt>853 THEN
clk_2<='1';
ELSE
clk_2<='0';
cnt:=0;
END IF;
END IF;
END PROCESS;
---------------------
SEND:PROCESS(clk_2) is
VARIABLE shift_cnt :INTEGER RANGE 0 to 15:=0;
BEGIN
IF RISING_EDGE(clk_2) THEN
--tx<=Transmit_buf(shift_cnt);
shift_cnt:=shift_cnt+1;
IF (shift_cnt=11) THEN shift_cnt:=0; END IF;
END IF;
END PROCESS;
Transmit_buf(0)<='0';
Transmit_buf(8 downto 1)<="10101010";
Transmit_buf(9)<='1';--parity_generator(Transmit_buf(8 downto 1));
Transmit_buf(15 downto 10)<=(others=>'1');
END BLOCK;
RECIVE :BLOCK ------------------------------------ R E C I V E ---------------------------------------------
SIGNAL x,z,buf2 : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL Rcive_buf : STD_LOGIC_VECTOR(15 downto 0);
TYPE resive_state is (IDEL,BUSY);
SIGNAL state : resive_state;
BEGIN
PROCESS(clk,rx) is
VARIABLE c_n_t :INTEGER RANGE 0 TO 1800;
VARIABLE Rx_puls_cnt :INTEGER RANGE 0 TO 16:=0;
BEGIN
IF FALLING_EDGE(rx) THEN
IF(state=IDEL) then
Z<=Z+'1';
END IF;
END IF;
IF RISING_EDGE(clk) THEN
IF (state=BUSY) THEN
c_n_t:=c_n_t+1;
IF(c_n_t=10 AND Rx_puls_cnt=0) THEN END IF;
IF c_n_t<854 THEN
clk_3<='0';
ELSIF c_n_t<1700 and c_n_t>853 THEN
clk_3<='1';
ELSE
Rx_puls_cnt:=Rx_puls_cnt+1;
c_n_t:=0;
IF(Rx_puls_cnt=10) then
state<=IDEL;
X<=z;
END IF;
END IF;
END IF;
IF(state=IDEL) then
IF(x/=z) then
state<=BUSY;
Rx_puls_cnt:=0;
c_n_t:=1;
ELSE
clk_3<='0';
END IF;
END IF;
END IF;
END PROCESS;
------------------------
RECIVE:PROCESS(clk_3) is
VARIABLE Recive_cnt :INTEGER RANGE 0 to 16:=0;
VARIABLE syncron_bit :INTEGER RANGE 0 to 1:=0;
BEGIN
IF RISING_EDGE(clk_3) THEN
-- IF( syncron_bit=0) THEN
-- START_BIT<=rx;
-- END IF;
--
-- IF (START_BIT='0') THEN
-- syncron_bit:=1; -- switch to get 8 bit state
-- IF (Recive_cnt<10) THEN
-- Rcive_buf(Recive_cnt)<=rx;
-- Recive_cnt:=Recive_cnt+1;
-- ELSE
-- START_BIT<='1';-- switch to get new data state
-- Recive_cnt:=0;-- reset counter
-- syncron_bit:=0;
-- END IF;
-- END IF;
Rcive_buf(Recive_cnt)<=rx;
Recive_cnt:=Recive_cnt+1;
IF (Recive_cnt=10) then
Recive_cnt:=0;
END IF;
END IF;
END PROCESS;
LED<=not(Rcive_buf(8 downto 1));
outp<=clk_3;
END BLOCK;
------------------------------------------------------------------------------------------------------------
END BEHAVIOR;
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