?? medical.map.rpt
字號:
+-----------------------------------------------------------------------------+--------------------+--------------------+
+-----------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+-----------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+-----------------------------------+
; medical.v ; yes ; User Verilog HDL File ; D:/TRY/medical----/FPGA/medical.v ;
; fenji.v ; yes ; User Verilog HDL File ; D:/TRY/medical----/FPGA/fenji.v ;
; led.v ; yes ; User Verilog HDL File ; D:/TRY/medical----/FPGA/led.v ;
+----------------------------------+-----------------+------------------------+-----------------------------------+
+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------------------+-------+
; Resource ; Usage ;
+-----------------------------------------------+-------+
; Estimated ALUTs Used ; 49 ;
; Dedicated logic registers ; 53 ;
; ; ;
; Estimated ALUTs Unavailable ; 5 ;
; ; ;
; Total combinational functions ; 49 ;
; Combinational ALUT usage by number of inputs ; ;
; -- 7 input functions ; 0 ;
; -- 6 input functions ; 0 ;
; -- 5 input functions ; 9 ;
; -- 4 input functions ; 11 ;
; -- <=3 input functions ; 29 ;
; ; ;
; Combinational ALUTs by mode ; ;
; -- normal mode ; 41 ;
; -- extended LUT mode ; 0 ;
; -- arithmetic mode ; 8 ;
; -- shared arithmetic mode ; 0 ;
; ; ;
; Estimated ALUT/register pairs used ; 54 ;
; ; ;
; Total registers ; 53 ;
; -- Dedicated logic registers ; 53 ;
; -- I/O registers ; 0 ;
; ; ;
; Estimated ALMs: partially or completely used ; 27 ;
; ; ;
; I/O pins ; 64 ;
; Maximum fan-out node ; rst ;
; Maximum fan-out ; 53 ;
; Total fan-out ; 352 ;
; Average fan-out ; 2.12 ;
+-----------------------------------------------+-------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+-------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+-------------------------+--------------+
; |medical ; 49 (33) ; 53 (29) ; 0 ; 0 ; 0 ; 0 ; 0 ; 64 ; 0 ; |medical ; work ;
; |fenji:fenji_u0| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |medical|fenji:fenji_u0 ; work ;
; |fenji:fenji_u1| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |medical|fenji:fenji_u1 ; work ;
; |fenji:fenji_u2| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |medical|fenji:fenji_u2 ; work ;
; |fenji:fenji_u3| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |medical|fenji:fenji_u3 ; work ;
; |fenji:fenji_u4| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |medical|fenji:fenji_u4 ; work ;
; |fenji:fenji_u5| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |medical|fenji:fenji_u5 ; work ;
; |fenji:fenji_u6| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |medical|fenji:fenji_u6 ; work ;
; |fenji:fenji_u7| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |medical|fenji:fenji_u7 ; work ;
; |led:led_u0| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |medical|led:led_u0 ; work ;
; |led:led_u1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |medical|led:led_u1 ; work ;
; |led:led_u2| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |medical|led:led_u2 ; work ;
; |led:led_u3| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |medical|led:led_u3 ; work ;
; |led:led_u4| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |medical|led:led_u4 ; work ;
; |led:led_u5| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |medical|led:led_u5 ; work ;
; |led:led_u6| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |medical|led:led_u6 ; work ;
; |led:led_u7| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |medical|led:led_u7 ; work ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+-------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 53 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 53 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Fri Apr 17 20:58:42 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off medical -c medical
Info: Found 1 design units, including 1 entities, in source file medical.v
Info: Found entity 1: medical
Info: Found 1 design units, including 1 entities, in source file fenji.v
Info: Found entity 1: fenji
Info: Found 1 design units, including 1 entities, in source file led.v
Info: Found entity 1: led
Info: Elaborating entity "medical" for the top level hierarchy
Info: Elaborating entity "fenji" for hierarchy "fenji:fenji_u0"
Info: Elaborating entity "led" for hierarchy "led:led_u0"
Warning (10036): Verilog HDL or VHDL warning at led.v(38): object "cnt" assigned a value but never read
Info: Implemented 124 device resources after synthesis - the final resource count might be different
Info: Implemented 19 input pins
Info: Implemented 45 output pins
Info: Implemented 60 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Allocated 143 megabytes of memory during processing
Info: Processing ended: Fri Apr 17 20:58:44 2009
Info: Elapsed time: 00:00:02
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