?? fenji.v
字號:
//this module is the fenji ,if out is 1 fenji have problem,if out is 0 fenji have no problem
module fenji(
clk,
rst,
in,
out
);
input clk;
input rst;
input in;
output out;
reg out;
always @(posedge clk or negedge rst)
begin
if(!rst)
out<=1'b0;
else out<=in;
end
endmodule
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