{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 17 20:57:19 2009 " "Info: Processing started: Fri Apr 17 20:57:19 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off medical -c medical " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off medical -c medical" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "medical.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file medical.v" { { "Info" "ISGN_ENTITY_NAME" "1 medical " "Info: Found entity 1: medical" {  } { { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 20 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fenji.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fenji.v" { { "Info" "ISGN_ENTITY_NAME" "1 fenji " "Info: Found entity 1: fenji" {  } { { "fenji.v" "" { Text "D:/TRY/medical----/FPGA/fenji.v" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file led.v" { { "Info" "ISGN_ENTITY_NAME" "1 led " "Info: Found entity 1: led" {  } { { "led.v" "" { Text "D:/TRY/medical----/FPGA/led.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "medical " "Info: Elaborating entity \"medical\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenji fenji:fenji_u0 " "Info: Elaborating entity \"fenji\" for hierarchy \"fenji:fenji_u0\"" {  } { { "medical.v" "fenji_u0" { Text "D:/TRY/medical----/FPGA/medical.v" 58 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led led:led_u0 " "Info: Elaborating entity \"led\" for hierarchy \"led:led_u0\"" {  } { { "medical.v" "led_u0" { Text "D:/TRY/medical----/FPGA/medical.v" 279 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "cnt led.v(38) " "Warning (10036): Verilog HDL or VHDL warning at led.v(38): object \"cnt\" assigned a value but never read" {  } { { "led.v" "" { Text "D:/TRY/medical----/FPGA/led.v" 38 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 258 -1 0 } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 258 -1 0 } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 258 -1 0 } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 258 -1 0 } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 258 -1 0 } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 258 -1 0 } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 258 -1 0 } } { "medical.v" "" { Text "D:/TRY/medical----/FPGA/medical.v" 258 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "124 " "Info: Implemented 124 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "19 " "Info: Implemented 19 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "45 " "Info: Implemented 45 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "60 " "Info: Implemented 60 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "143 " "Info: Allocated 143 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 17 20:57:21 2009 " "Info: Processing ended: Fri Apr 17 20:57:21 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}