Classic Timing Analyzer report for medical
Fri Apr 17 20:59:07 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. Clock Setup: 'clk2'
  7. tsu
  8. tco
  9. th
 10. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                          ;
+------------------------------+-------+---------------+------------------------------------------------+--------------+--------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From         ; To                 ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+--------------+--------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 3.144 ns                                       ; err[5]       ; fenji:fenji_u5|out ; --         ; clk      ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 7.344 ns                                       ; cnt[3]~reg0  ; cnt[3]             ; clk2       ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -1.831 ns                                      ; err[0]       ; fenji:fenji_u0|out ; --         ; clk      ; 0            ;
; Clock Setup: 'clk2'          ; N/A   ; None          ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[3]~reg0  ; cnt[2]~reg0        ; clk2       ; clk2     ; 0            ;
; Clock Setup: 'clk'           ; N/A   ; None          ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cntt[5]~reg0 ; cntt[3]~reg0       ; clk        ; clk      ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;              ;                    ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+--------------+--------------------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP2S15F484C3       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; clk2            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                             ;
+-------+------------------------------------------------+--------------------+----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From               ; To                   ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------------------+----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cntt[5]~reg0       ; cntt[3]~reg0         ; clk        ; clk      ; None                        ; None                      ; 1.307 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cntt[5]~reg0       ; cntt[5]~reg0         ; clk        ; clk      ; None                        ; None                      ; 1.272 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cntt[2]~reg0       ; cntt[3]~reg0         ; clk        ; clk      ; None                        ; None                      ; 1.249 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cntt[2]~reg0       ; cntt[5]~reg0         ; clk        ; clk      ; None                        ; None                      ; 1.214 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cntt[0]~reg0       ; cntt[5]~reg0         ; clk        ; clk      ; None                        ; None                      ; 1.189 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cntt[0]~reg0       ; cntt[3]~reg0         ; clk        ; clk      ; None                        ; None                      ; 1.186 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cntt[1]~reg0       ; cntt[5]~reg0         ; clk        ; clk      ; None                        ; None                      ; 1.154 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cntt[3]~reg0       ; cntt[5]~reg0         ; clk        ; clk      ; None                        ; None                      ; 1.153 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cntt[1]~reg0       ; cntt[3]~reg0         ; clk        ; clk      ; None                        ; None                      ; 1.151 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cntt[3]~reg0       ; cntt[3]~reg0         ; clk        ; clk      ; None                        ; None                      ; 1.122 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cntt[4]~reg0       ; cntt[5]~reg0         ; clk        ; clk      ; None                        ; None                      ; 1.049 ns                ;