--參加比較的矢量寬度均為n+1，該電路的3個(gè)輸出為x1（當(dāng)a>b時(shí)輸出為1）,x2（當(dāng)a=b時(shí)輸出為1）,x3（當(dāng)a<b時(shí)輸出為1）
---下面的代碼中使用了std-logic-arith包集，它對(duì)于有符號(hào)和無(wú)符號(hào)類型數(shù)據(jù)的操作非常重要
----------------signed comparator-------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity bijiaoqi is
   generic(n : integer := 7);
   port( a,b: in signed (n downto 0);----注意signed的寫法
        x1,x2,x3: out std_logic); 
end bijiaoqi;
architecture bijiaoqi of bijiaoqi is
begin 
 x1 <= '1' when a>b else '0';
 x2 <= '1' when a=b else '0';
 x3 <= '1' when a<b else '0';
end bijiaoqi;