library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity dac_ds is

port(reset :in std_logic;

clk :in std_logic;

din :in std_logic_vector(7 downto 0);--Signed integer

dout :out std_logic);

end dac_ds;

architecture arch_dac_ds of dac_ds is

signal error :std_logic_vector(9 downto 0);--Error accumulator is 2 bits larger

constant zeros:std_logic_vector(7 downto 0):=(others=>'0');

begin

process(reset,clk,din)

variable val :std_logic_vector(9 downto 0);

begin

if reset='1'then

error<=(others=>'0');

dout<='0';

elsif clk'event and clk='1' then

--val:=din+error;din is sign extended to nbits+2

val:=(din(din'high)&din(din'high)&din)+error;

if val(val'high)='0'then

dout<='1';

error<=val+("11"& zeros);

else

dout<='0';

error<=val+("01"&zeros);

end if;

end if;

end process;

end arch_dac_ds;