?? project3.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity project3 is
port(ctrl:in std_logic;
row,col:out std_logic_vector(7 downto 0);
clk:in std_logic;
alarm:out std_logic);
end;
architecture behave of project3 is
constant U1:integer:=49999;
constant U2:integer:=24999999;
signal col0,col1,col2,col3,col4,col5,col6,col7: std_logic_vector(7 downto 0);
signal count:std_logic_vector( 3 downto 0);
signal clk1,clk2:std_logic;
signal ctrl_c: integer range 0 to 2;
signal cou1:std_logic;
begin
process(clk)
variable count1:integer range 0 to U1;
variable count2:integer range 0 to U2;
begin
if(clk'event and clk='0') then
if(count1=U1) then
clk1<=not clk1;
count1:=0;
else
count1:=count1+1;
end if;
if(count2=U2) then
clk2<=not clk2;
count2:=0;
else
count2:=count2+1;
end if;
end if;
end process;
process(clk1,ctrl)
variable cou: integer range 0 to 4;
begin
if(ctrl='1') then
if(clk1'event and clk1='0') then
if(cou=4) then
cou1<='1';
else
cou:=cou+1;
end if;
end if;
else
cou:=0;
cou1<='0';
end if;
if( cou1'event and cou1='1' ) then
if(ctrl_c=2) then
ctrl_c<=0;
else
ctrl_c<=ctrl_c+1;
end if;
end if;
end process;
process(clk2,ctrl_c)
begin
if(ctrl_c=0) then
if(count="1010") then
count<="0000";
end if;
elsif (ctrl_c=1) then
if(clk2'event and clk2='0') then
if(count="1001") then
alarm<='1';
else
count<=count+1;
alarm<='0';
col7<="00000000";
end if;
end if;
elsif(ctrl_c=2) then
alarm<='0';
count<="1010";
end if;
case count is
when "0000"=> --9
col0<="00000000";
col1<="01110010";
col2<="01010010";
col3<="01010010";
col4<="01010010";
col5<="01010010";
col6<="01111110";
col7<="00000000";
when "0001"=> --8
col0<="00000000";
col1<="01111110";
col2<="01010010";
col3<="01010010";
col4<="01010010";
col5<="01010010";
col6<="01111110";
col7<="00000000";
when "0010"=> --7
col0<="00000000";
col1<="01000000";
col2<="01000000";
col3<="01000000";
col4<="01000000";
col5<="01000000";
col6<="01111110";
col7<="00000000";
when "0011"=> --6
col0<="00000000";
col1<="01111110";
col2<="01010010";
col3<="01010010";
col4<="01010010";
col5<="01010010";
col6<="01011110";
col7<="00000000";
when "0100"=> --5
col0<="00000000";
col1<="01110010";
col2<="01010010";
col3<="01010010";
col4<="01010010";
col5<="01010010";
col6<="01011110";
col7<="00000000";
when "0101"=> --4
col0<="00000000";
col1<="01110000";
col2<="00010000";
col3<="00010000";
col4<="01111110";
col5<="00010000";
col6<="00010000";
col7<="00000000";
when "0110"=> --3
col0<="00000000";
col1<="01010010";
col2<="01010010";
col3<="01010010";
col4<="01010010";
col5<="01010010";
col6<="01111110";
col7<="00000000";
when "0111"=> --2
col0<="00000000";
col1<="01011110";
col2<="01010010";
col3<="01010010";
col4<="01010010";
col5<="01010010";
col6<="01110010";
col7<="00000000";
when "1000"=> --1
col0<="00000000";
col1<="00000000";
col2<="00000000";
col3<="01111110";
col4<="00000000";
col5<="00000000";
col6<="00000000";
col7<="00000000";
when "1001"=> --0
col0<="00000000";
col1<="01111110";
col2<="01000010";
col3<="01000010";
col4<="01000010";
col5<="01000010";
col6<="01111110";
col7<="00000001";
when others=> --0'
col0<="00000000";
col1<="01111110";
col2<="01000010";
col3<="01000010";
col4<="01000010";
col5<="01000010";
col6<="01111110";
col7<="00000000";
end case ;
end process;
process(clk1,count)
variable count3:integer range 0 to 7;
begin
if(clk1'event and clk1='0') then
case count3 is
when 0=>
row<=col0;
col<="01111111";
when 1=>
row<=col1;
col<="10111111";
when 2=>
row<=col2;
col<="11011111";
when 3=>
row<=col3;
col<="11101111";
when 4=>
row<=col4;
col<="11110111";
when 5=>
row<=col5;
col<="11111011";
when 6=>
row<=col6;
col<="11111101";
when 7=>
row<=col7;
col<="11111110";
end case;
count3:=count3+1;
end if;
end process;
end ;
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