module output_sw (
  rst           ,
  clk           ,
  inv_i         ,
  exp_clr       ,
  frame_out_enb ,
  frame_out_sop ,
  frame_out_eop ,
  wr_stage_cmplt,
  shift_ctrl    ,
  fft_real_in   ,
  fft_image_in  ,
  fft_real_out  ,
  fft_image_out ,
  exponent_out  ,
  master_source_enb ,
  master_source_sop ,
  master_source_eop 
);

input rst, clk;
input inv_i, exp_clr;
input wr_stage_cmplt;
input frame_out_enb,frame_out_sop,frame_out_eop;
input [1:0] shift_ctrl;
input [11:0] fft_real_in, fft_image_in;
output [9:0] fft_real_out, fft_image_out;
output [5:0] exponent_out;
output master_source_enb,master_source_sop,master_source_eop;

reg [9:0] fft_real_out,fft_image_out;
reg [5:0] exponent_out;
reg master_source_enb,master_source_sop,master_source_eop;

wire [11:0] image_in;

assign image_in = (inv_i) ? (~fft_image_in + 1'b1) : fft_image_in;

always @(posedge rst or posedge clk) begin
  if(rst) begin
	  fft_real_out  <= 10'h0; 
	  fft_image_out <= 10'h0; 
  end
  else if(frame_out_enb) begin
  	  case(shift_ctrl)
		  2'b00 : begin  
	                  fft_real_out  <= fft_real_in[9:0]; 
	                  fft_image_out <= image_in[9:0]; 
		  end
		  2'b01 : begin  
	                  fft_real_out  <= (fft_real_in[11]) ? (fft_real_in[10:1]) : (fft_real_in[10:1] + {9'b0_0000_0000, fft_real_in[0]}) ; 
	                  fft_image_out <= (   image_in[11]) ? (   image_in[10:1]) : (   image_in[10:1] + {9'b0_0000_0000,    image_in[0]}) ; 
		  end
		  2'b10 : begin  
	                  fft_real_out  <= (fft_real_in[11:2] )   ; 
	                  fft_image_out <= (   image_in[11:2] )   ; 
		  end
		  default : begin
	                  fft_real_out  <= 10'h000; 
	                  fft_image_out <= 10'h000; 
		  end
	  endcase
  end
end

reg exp_sub_enb;

always @(posedge rst or posedge clk) begin
  if(rst) begin
	  exp_sub_enb <= 1'b0;
  end
  else begin
	  exp_sub_enb <= wr_stage_cmplt;
  end
end
  
always @(posedge rst or posedge clk) begin
  if(rst) begin
	  exponent_out <= 6'b00_0000;
  end
  else begin 
	  if(exp_clr)
	  	exponent_out <= (inv_i) ? 6'b00_1011 : 6'b00_0000;  // 2^11=2048
          else if(exp_sub_enb)
	  	exponent_out <= exponent_out - {4'b0000,shift_ctrl[1:0]};
  end
end

always @(posedge rst or posedge clk) begin
  if(rst) begin
	  master_source_enb <= 1'b0;
	  master_source_sop <= 1'b0;
	  master_source_eop <= 1'b0;
  end
  else begin
	  master_source_enb <= frame_out_enb;
	  master_source_sop <= frame_out_sop;
	  master_source_eop <= frame_out_eop;
  end
end

endmodule