library verilog;use verilog.vl_types.all;entity comp is    port(        a1              : in     vl_logic_vector(3 downto 0);        a2              : in     vl_logic_vector(3 downto 0);        min             : out    vl_logic_vector(3 downto 0);        max             : out    vl_logic_vector(3 downto 0)    );end comp;