?? rsmm.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RSm is
port( CLK:in std_logic;
RS:out std_logic
);
end entity RSm;
architecture one of RSm is
variable count : integer range 0 to 10;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF count < 7 THEN
count := count + 1 ;
RS<='1';
ELSE count := 0 ;
RS<='0';
END IF ;
END IF ;
END PROCESS ;
end architecture one;
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