?? cpm.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cpm is
port( CLK:in std_logic;
R:in std_logic;
CP:out std_logic
);
end entity cpm;
architecture one of cpm is
signal D1,D2:std_logic;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
D1<=D2;
D2<=R;
END IF;
END PROCESS;
CP<=D1;
END ONE;
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