?? adder4bit.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder4bit is
port(cin:in std_logic;
a,b:in std_logic_vector(3 downto 0);
s:out std_logic_vector(3 downto 0);
cout:out std_logic);
end adder4bit;
architecture beh of adder4bit is
signal sint:std_logic_vector(4 downto 0);
signal aa,bb:std_logic_vector(4 downto 0);
begin
aa<='0' & a(3 downto 0); --4位加數矢量擴為5位,提供進位空間
bb<='0' & b(3 downto 0);
sint<=aa+bb+cin;
s(3 downto 0)<=sint(3 downto 0);
cout<=sint(4);
end beh;
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