LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PULSE IS
    PORT (   CLK  : IN STD_LOGIC;
               D  : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
             FOUT : OUT STD_LOGIC  );
END PULSE;
ARCHITECTURE beh OF PULSE IS
    SIGNAL   FULL : STD_LOGIC;
BEGIN
  P_REG: PROCESS(CLK)
   VARIABLE CNT8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
   BEGIN           
      IF CLK'EVENT AND CLK = '1' THEN
            IF CNT8 = "11111111" THEN   
              CNT8 := D;       --當CNT8計數(shù)計滿時，輸入數(shù)據D被同步預置給計數(shù)器CNT8    
              FULL <= '1';                  --同時使溢出標志信號FULL輸出為高電平               
                ELSE   CNT8 := CNT8 + 1;  --否則繼續(xù)作加1計數(shù)
                         FULL <= '0';       --且輸出溢出標志信號FULL為低電平       
            END IF;
	  END IF;
    END PROCESS P_REG ;
   P_DIV: PROCESS(FULL)
     VARIABLE CNT2 : STD_LOGIC;
   BEGIN
   IF FULL'EVENT AND FULL = '1' 
       THEN  CNT2 := NOT CNT2;    --如果溢出標志信號FULL為高電平，D觸發(fā)器輸出取反
         IF CNT2 = '1' THEN  
FOUT <= '1'; 
           ELSE      
FOUT <= '0';
        END IF;
   END IF;
    END PROCESS P_DIV ;
END beh;