LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY s_machine IS
  PORT ( clk,reset    : IN STD_LOGIC;
          state_inputs : IN STD_LOGIC_VECTOR (0 TO 1);
          comb_outputs : OUT INTEGER RANGE 0 TO 15 );
END s_machine;
ARCHITECTURE behv OF s_machine IS
  TYPE FSM_ST IS (s0, s1, s2, s3);  
  SIGNAL current_state, next_state: FSM_ST;
BEGIN
 REG: PROCESS (reset,clk)                  
  BEGIN
    IF reset = '1' THEN   current_state <= s0;        --復位             
    ELSIF clk='1' AND clk'EVENT THEN   
      current_state <= next_state; 
    END IF;
  END PROCESS;     
COM:PROCESS(current_state, state_Inputs)
BEGIN
    CASE current_state IS                                 --狀態轉換關系
      WHEN s0 => comb_outputs<= 5;     
        IF state_inputs = "00" THEN  next_state<=s0;                       
           ELSE  next_state<=s1;    
        END IF;
      WHEN s1 =>  comb_outputs<= 8;
        IF state_inputs = "00" THEN  next_state<=s1;    
        ELSE  next_state<=s2;   
        END IF;
      WHEN s2 =>   comb_outputs<= 12;  
        IF state_inputs = "11" THEN  next_state <= s0;
        ELSE  next_state <= s3; 
        END IF;
      WHEN s3 =>  comb_outputs <= 14;
        IF state_inputs = "11" THEN  next_state <= s3; 
        ELSE  next_state <= s0;   
        END IF;
    END case;
  END PROCESS;      
END behv;