-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--W1_select_n_to_the_cfi_flash_0 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|select_n_to_the_cfi_flash_0
W1_select_n_to_the_cfi_flash_0 = DFFEAS(W1L62, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_readn is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_readn
W1_tri_state_bridge_0_readn = DFFEAS(W1L85, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_write_n_to_the_cfi_flash_0 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|write_n_to_the_cfi_flash_0
W1_write_n_to_the_cfi_flash_0 = DFFEAS(W1L87, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--YB1_safe_q[9] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[9]
YB1_safe_q[9] = DFFEAS(YB1_counter_comb_bita9, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[8] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[8]
YB1_safe_q[8] = DFFEAS(YB1_counter_comb_bita8, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[7] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[7]
YB1_safe_q[7] = DFFEAS(YB1_counter_comb_bita7, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[6] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[6]
YB1_safe_q[6] = DFFEAS(YB1_counter_comb_bita6, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[5] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[5]
YB1_safe_q[5] = DFFEAS(YB1_counter_comb_bita5, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[4] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[4]
YB1_safe_q[4] = DFFEAS(YB1_counter_comb_bita4, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[3] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[3]
YB1_safe_q[3] = DFFEAS(YB1_counter_comb_bita3, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[2] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[2]
YB1_safe_q[2] = DFFEAS(YB1_counter_comb_bita2, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[1] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[1]
YB1_safe_q[1] = DFFEAS(YB1_counter_comb_bita1, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_safe_q[0] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|safe_q[0]
YB1_safe_q[0] = DFFEAS(YB1_counter_comb_bita0, CLOCK_50, KEY[0],  , !YB1L20,  ,  ,  ,  );


--YB1_counter_comb_bita0 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita0
YB1_counter_comb_bita0 = YB1_safe_q[0] $ VCC;

--YB1L2 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita0~COUT
YB1L2 = CARRY(YB1_safe_q[0]);


--YB1_counter_comb_bita1 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita1
YB1_counter_comb_bita1 = YB1_safe_q[1] & !YB1L2 # !YB1_safe_q[1] & (YB1L2 # GND);

--YB1L4 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita1~COUT
YB1L4 = CARRY(!YB1L2 # !YB1_safe_q[1]);


--YB1_counter_comb_bita2 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita2
YB1_counter_comb_bita2 = YB1_safe_q[2] & (YB1L4 $ GND) # !YB1_safe_q[2] & !YB1L4 & VCC;

--YB1L6 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita2~COUT
YB1L6 = CARRY(YB1_safe_q[2] & !YB1L4);


--YB1_counter_comb_bita3 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita3
YB1_counter_comb_bita3 = YB1_safe_q[3] & !YB1L6 # !YB1_safe_q[3] & (YB1L6 # GND);

--YB1L8 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita3~COUT
YB1L8 = CARRY(!YB1L6 # !YB1_safe_q[3]);


--YB1_counter_comb_bita4 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita4
YB1_counter_comb_bita4 = YB1_safe_q[4] & (YB1L8 $ GND) # !YB1_safe_q[4] & !YB1L8 & VCC;

--YB1L10 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita4~COUT
YB1L10 = CARRY(YB1_safe_q[4] & !YB1L8);


--YB1_counter_comb_bita5 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita5
YB1_counter_comb_bita5 = YB1_safe_q[5] & !YB1L10 # !YB1_safe_q[5] & (YB1L10 # GND);

--YB1L12 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita5~COUT
YB1L12 = CARRY(!YB1L10 # !YB1_safe_q[5]);


--YB1_counter_comb_bita6 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita6
YB1_counter_comb_bita6 = YB1_safe_q[6] & (YB1L12 $ GND) # !YB1_safe_q[6] & !YB1L12 & VCC;

--YB1L14 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita6~COUT
YB1L14 = CARRY(YB1_safe_q[6] & !YB1L12);


--YB1_counter_comb_bita7 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita7
YB1_counter_comb_bita7 = YB1_safe_q[7] & !YB1L14 # !YB1_safe_q[7] & (YB1L14 # GND);

--YB1L16 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita7~COUT
YB1L16 = CARRY(!YB1L14 # !YB1_safe_q[7]);


--YB1_counter_comb_bita8 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita8
YB1_counter_comb_bita8 = YB1_safe_q[8] & (YB1L16 $ GND) # !YB1_safe_q[8] & !YB1L16 & VCC;

--YB1L18 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita8~COUT
YB1L18 = CARRY(YB1_safe_q[8] & !YB1L16);


--YB1_counter_comb_bita9 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita9
YB1_counter_comb_bita9 = YB1_safe_q[9] & !YB1L18 # !YB1_safe_q[9] & (YB1L18 # GND);

--YB1L22 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita9~COUT
YB1L22 = CARRY(!YB1L18 # !YB1_safe_q[9]);


--YB1L20 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_8bc:auto_generated|counter_comb_bita9~9
YB1L20 = !YB1L22;


--C1_inst4 is delay_reset_block:inst3|inst4
C1_inst4 = !KEY[0] # !YB1L20;


--W1_tri_state_bridge_0_address[21] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[21]
W1_tri_state_bridge_0_address[21] = DFFEAS(W1L84, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[20] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[20]
W1_tri_state_bridge_0_address[20] = DFFEAS(W1L83, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[19] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[19]
W1_tri_state_bridge_0_address[19] = DFFEAS(W1L82, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[18] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[18]
W1_tri_state_bridge_0_address[18] = DFFEAS(W1L81, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[17] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[17]
W1_tri_state_bridge_0_address[17] = DFFEAS(W1L80, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[16] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[16]
W1_tri_state_bridge_0_address[16] = DFFEAS(W1L79, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[15] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[15]
W1_tri_state_bridge_0_address[15] = DFFEAS(W1L78, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[14] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[14]
W1_tri_state_bridge_0_address[14] = DFFEAS(W1L77, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[13] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[13]
W1_tri_state_bridge_0_address[13] = DFFEAS(W1L76, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[12] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[12]
W1_tri_state_bridge_0_address[12] = DFFEAS(W1L75, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[11] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[11]
W1_tri_state_bridge_0_address[11] = DFFEAS(W1L74, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[10] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[10]
W1_tri_state_bridge_0_address[10] = DFFEAS(W1L73, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[9] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[9]
W1_tri_state_bridge_0_address[9] = DFFEAS(W1L72, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[8] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[8]
W1_tri_state_bridge_0_address[8] = DFFEAS(W1L71, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[7] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[7]
W1_tri_state_bridge_0_address[7] = DFFEAS(W1L70, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[6] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[6]
W1_tri_state_bridge_0_address[6] = DFFEAS(W1L69, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[5] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[5]
W1_tri_state_bridge_0_address[5] = DFFEAS(W1L68, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[4] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[4]
W1_tri_state_bridge_0_address[4] = DFFEAS(W1L67, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[3] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[3]
W1_tri_state_bridge_0_address[3] = DFFEAS(W1L66, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[2] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[2]
W1_tri_state_bridge_0_address[2] = DFFEAS(W1L65, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[1]
W1_tri_state_bridge_0_address[1] = DFFEAS(W1L64, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_tri_state_bridge_0_address[0] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_address[0]
W1_tri_state_bridge_0_address[0] = DFFEAS(W1L63, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--A1L6 is altera_internal_jtag~TDO
A1L6 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L14);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L14);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L14);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = CYCLONEII_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , D1L14);


--W1_tri_state_bridge_0_avalon_slave_arb_addend[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[1]
W1_tri_state_bridge_0_avalon_slave_arb_addend[1] = DFFEAS(W1L118, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1_F_pc[20] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[20]
H1_F_pc[20] = AMPP_FUNCTION(CLOCK_50, H1L593, E1_data_out, H1_W_valid);


--H1_i_read is DE2_Board:inst|cpu_0:the_cpu_0|i_read
H1_i_read = AMPP_FUNCTION(CLOCK_50, H1_i_read_nxt, E1_data_out);


--W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1]
W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] = DFFEAS(W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0]
W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0] = DFFEAS(W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register_in, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L28 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_0_s1~57
W1L28 = H1_F_pc[20] & !H1_i_read & !W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[1] & !W1_cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1_shift_register[0];


--W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_slavearbiterlockenable
W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable = DFFEAS(W1L143, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1
W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 = DFFEAS(W1L59, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1_W_alu_result[22] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[22]
H1_W_alu_result[22] = AMPP_FUNCTION(CLOCK_50, H1L735, H1_E_shift_rot_result[22], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_d_read is DE2_Board:inst|cpu_0:the_cpu_0|d_read
H1_d_read = AMPP_FUNCTION(CLOCK_50, H1_d_read_nxt, E1_data_out);


--AB1_d_write is DE2_Board:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|d_write
AB1_d_write = AMPP_FUNCTION(CLOCK_50, H1_d_write_nxt, E1_data_out);