--W1_cpu_0_data_master_requests_cfi_flash_0_s1 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_requests_cfi_flash_0_s1
W1_cpu_0_data_master_requests_cfi_flash_0_s1 = H1_W_alu_result[22] & (H1_d_read # AB1_d_write);


--W1L29 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_qualified_request_cfi_flash_0_s1~58
W1L29 = W1L28 & (!W1_cpu_0_data_master_requests_cfi_flash_0_s1 # !W1_last_cycle_cpu_0_data_master_granted_slave_cfi_flash_0_s1 # !W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable);


--W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1
W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 = DFFEAS(W1L61, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L135 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_firsttransfer~99
W1L135 = H1_F_pc[20] & W1_last_cycle_cpu_0_instruction_master_granted_slave_cfi_flash_0_s1 & !H1_i_read;


--W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1]
W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] = DFFEAS(W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0], CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0]
W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0] = DFFEAS(W1L25, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L19 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~176
W1L19 = H1_d_read & (W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[1] # W1_cpu_0_data_master_read_data_valid_cfi_flash_0_s1_shift_register[0]);


--W1L20 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~177
W1L20 = W1_cpu_0_data_master_requests_cfi_flash_0_s1 & !W1L19 & (!W1L135 # !W1_tri_state_bridge_0_avalon_slave_slavearbiterlockenable);


--J1_cpu_0_data_master_dbs_address[0] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[0]
J1_cpu_0_data_master_dbs_address[0] = DFFEAS(J1L8, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--H1_d_byteenable[3] is DE2_Board:inst|cpu_0:the_cpu_0|d_byteenable[3]
H1_d_byteenable[3] = AMPP_FUNCTION(CLOCK_50, H1L183, E1_data_out);


--H1_d_byteenable[1] is DE2_Board:inst|cpu_0:the_cpu_0|d_byteenable[1]
H1_d_byteenable[1] = AMPP_FUNCTION(CLOCK_50, H1L181, E1_data_out);


--J1_cpu_0_data_master_dbs_address[1] is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_dbs_address[1]
J1_cpu_0_data_master_dbs_address[1] = DFFEAS(J1L10, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L17 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_byteenable_cfi_flash_0_s1~333
W1L17 = J1_cpu_0_data_master_dbs_address[0] & (J1_cpu_0_data_master_dbs_address[1] & H1_d_byteenable[3] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_byteenable[1]));


--H1_d_byteenable[2] is DE2_Board:inst|cpu_0:the_cpu_0|d_byteenable[2]
H1_d_byteenable[2] = AMPP_FUNCTION(CLOCK_50, H1L182, E1_data_out);


--H1_d_byteenable[0] is DE2_Board:inst|cpu_0:the_cpu_0|d_byteenable[0]
H1_d_byteenable[0] = AMPP_FUNCTION(CLOCK_50, H1L185, E1_data_out);


--T1L5 is DE2_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_byteenable_payload_buffer_s1[0]~60
T1L5 = J1_cpu_0_data_master_dbs_address[1] & H1_d_byteenable[2] # !J1_cpu_0_data_master_dbs_address[1] & (H1_d_byteenable[0]);


--W1L18 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_byteenable_cfi_flash_0_s1~334
W1L18 = W1L17 # T1L5 & !J1_cpu_0_data_master_dbs_address[0];


--J1_cpu_0_data_master_no_byte_enables_and_last_term is DE2_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|cpu_0_data_master_no_byte_enables_and_last_term
J1_cpu_0_data_master_no_byte_enables_and_last_term = DFFEAS(J1L179, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L21 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_data_master_qualified_request_cfi_flash_0_s1~178
W1L21 = W1L20 & (W1L18 & !J1_cpu_0_data_master_no_byte_enables_and_last_term # !AB1_d_write);


--W1_tri_state_bridge_0_avalon_slave_arb_addend[0] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_arb_addend[0]
W1_tri_state_bridge_0_avalon_slave_arb_addend[0] = DFFEAS(W1L115, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L62 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_select_n_to_the_cfi_flash_0~0
W1L62 = W1_tri_state_bridge_0_avalon_slave_arb_addend[1] & (W1L29 # W1L21) # !W1_tri_state_bridge_0_avalon_slave_arb_addend[1] & !W1_tri_state_bridge_0_avalon_slave_arb_addend[0] & (W1L29 # W1L21);


--E1_data_out is DE2_Board:inst|DE2_Board_reset_clk_domain_synch_module:DE2_Board_reset_clk_domain_synch|data_out
E1_data_out = DFFEAS(E1_data_in_d1, CLOCK_50, !C1_inst4,  ,  ,  ,  ,  ,  );


--W1L27 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cpu_0_instruction_master_granted_cfi_flash_0_s1~29
W1L27 = W1L29 & (W1_tri_state_bridge_0_avalon_slave_arb_addend[1] & !W1L21 # !W1_tri_state_bridge_0_avalon_slave_arb_addend[0]);


--W1L137 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_grant_vector[1]~31
W1L137 = W1L21 & (W1_tri_state_bridge_0_avalon_slave_arb_addend[1] # !W1L29 & !W1_tri_state_bridge_0_avalon_slave_arb_addend[0]);


--W1_cfi_flash_0_s1_in_a_read_cycle is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_in_a_read_cycle
W1_cfi_flash_0_s1_in_a_read_cycle = W1L27 # H1_d_read & W1L137;


--W1_cfi_flash_0_s1_wait_counter[3] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[3]
W1_cfi_flash_0_s1_wait_counter[3] = DFFEAS(W1L8, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_d1_reasons_to_wait is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_reasons_to_wait
W1_d1_reasons_to_wait = DFFEAS(W1L134, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L131 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_avalon_slave_begins_xfer~36
W1L131 = !W1_d1_reasons_to_wait & (W1L29 # W1L21);


--W1L85 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_readn~1
W1L85 = W1_cfi_flash_0_s1_in_a_read_cycle & !W1_cfi_flash_0_s1_wait_counter[3] & !W1L131;


--W1_in_a_write_cycle is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|in_a_write_cycle
W1_in_a_write_cycle = !W1L137 # !AB1_d_write;


--W1_cfi_flash_0_s1_wait_counter[2] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[2]
W1_cfi_flash_0_s1_wait_counter[2] = DFFEAS(W1L7, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1_cfi_flash_0_s1_wait_counter[1] is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_wait_counter[1]
W1_cfi_flash_0_s1_wait_counter[1] = DFFEAS(W1L5, CLOCK_50, E1_data_out,  ,  ,  ,  ,  ,  );


--W1L86 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_write_n_to_the_cfi_flash_0~104
W1L86 = !W1_cfi_flash_0_s1_wait_counter[2] & !W1_cfi_flash_0_s1_wait_counter[1];


--W1L87 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_write_n_to_the_cfi_flash_0~105
W1L87 = !W1_in_a_write_cycle & !W1L131 & (W1_cfi_flash_0_s1_wait_counter[3] $ !W1L86);


--H1_W_alu_result[21] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[21]
H1_W_alu_result[21] = AMPP_FUNCTION(CLOCK_50, H1L732, H1_E_shift_rot_result[21], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[19] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[19]
H1_F_pc[19] = AMPP_FUNCTION(CLOCK_50, H1L586, H1L815, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L84 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[21]~198
W1L84 = W1L137 & H1_W_alu_result[21] # !W1L137 & (H1_F_pc[19]);


--H1_W_alu_result[20] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[20]
H1_W_alu_result[20] = AMPP_FUNCTION(CLOCK_50, H1L729, H1_E_shift_rot_result[20], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[18] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[18]
H1_F_pc[18] = AMPP_FUNCTION(CLOCK_50, H1L583, H1L813, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L83 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[20]~199
W1L83 = W1L137 & H1_W_alu_result[20] # !W1L137 & (H1_F_pc[18]);


--H1_W_alu_result[19] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[19]
H1_W_alu_result[19] = AMPP_FUNCTION(CLOCK_50, H1L726, H1_E_shift_rot_result[19], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[17] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[17]
H1_F_pc[17] = AMPP_FUNCTION(CLOCK_50, H1L580, H1L811, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L82 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[19]~200
W1L82 = W1L137 & H1_W_alu_result[19] # !W1L137 & (H1_F_pc[17]);


--H1_W_alu_result[18] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[18]
H1_W_alu_result[18] = AMPP_FUNCTION(CLOCK_50, H1L723, H1_E_shift_rot_result[18], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[16] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[16]
H1_F_pc[16] = AMPP_FUNCTION(CLOCK_50, H1L577, H1L809, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L81 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[18]~201
W1L81 = W1L137 & H1_W_alu_result[18] # !W1L137 & (H1_F_pc[16]);


--H1_W_alu_result[17] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[17]
H1_W_alu_result[17] = AMPP_FUNCTION(CLOCK_50, H1L720, H1_E_shift_rot_result[17], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[15] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[15]
H1_F_pc[15] = AMPP_FUNCTION(CLOCK_50, H1L574, H1L807, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L80 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[17]~202
W1L80 = W1L137 & H1_W_alu_result[17] # !W1L137 & (H1_F_pc[15]);


--H1_W_alu_result[16] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[16]
H1_W_alu_result[16] = AMPP_FUNCTION(CLOCK_50, H1L717, H1_E_shift_rot_result[16], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[14] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[14]
H1_F_pc[14] = AMPP_FUNCTION(CLOCK_50, H1L571, H1L805, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L79 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[16]~203
W1L79 = W1L137 & H1_W_alu_result[16] # !W1L137 & (H1_F_pc[14]);


--H1_W_alu_result[15] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[15]
H1_W_alu_result[15] = AMPP_FUNCTION(CLOCK_50, H1L714, H1_E_shift_rot_result[15], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[13] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[13]
H1_F_pc[13] = AMPP_FUNCTION(CLOCK_50, H1L568, H1L803, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L78 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[15]~204
W1L78 = W1L137 & H1_W_alu_result[15] # !W1L137 & (H1_F_pc[13]);


--H1_W_alu_result[14] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[14]
H1_W_alu_result[14] = AMPP_FUNCTION(CLOCK_50, H1L711, H1_E_shift_rot_result[14], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[12] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[12]
H1_F_pc[12] = AMPP_FUNCTION(CLOCK_50, H1L565, H1L801, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L77 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[14]~205
W1L77 = W1L137 & H1_W_alu_result[14] # !W1L137 & (H1_F_pc[12]);


--H1_W_alu_result[13] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[13]
H1_W_alu_result[13] = AMPP_FUNCTION(CLOCK_50, H1L708, H1_E_shift_rot_result[13], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[11] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[11]
H1_F_pc[11] = AMPP_FUNCTION(CLOCK_50, H1L562, H1L799, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L76 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[13]~206
W1L76 = W1L137 & H1_W_alu_result[13] # !W1L137 & (H1_F_pc[11]);


--H1_W_alu_result[12] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[12]
H1_W_alu_result[12] = AMPP_FUNCTION(CLOCK_50, H1L705, H1_E_shift_rot_result[12], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[10] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[10]
H1_F_pc[10] = AMPP_FUNCTION(CLOCK_50, H1L559, H1L797, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L75 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[12]~207
W1L75 = W1L137 & H1_W_alu_result[12] # !W1L137 & (H1_F_pc[10]);


--H1_W_alu_result[11] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[11]
H1_W_alu_result[11] = AMPP_FUNCTION(CLOCK_50, H1L702, H1_E_shift_rot_result[11], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[9] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[9]
H1_F_pc[9] = AMPP_FUNCTION(CLOCK_50, H1L556, H1L795, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L74 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[11]~208
W1L74 = W1L137 & H1_W_alu_result[11] # !W1L137 & (H1_F_pc[9]);


--H1_W_alu_result[10] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[10]
H1_W_alu_result[10] = AMPP_FUNCTION(CLOCK_50, H1L699, H1_E_shift_rot_result[10], E1_data_out, H1L127, H1_R_ctrl_shift_rot);


--H1_F_pc[8] is DE2_Board:inst|cpu_0:the_cpu_0|F_pc[8]
H1_F_pc[8] = AMPP_FUNCTION(CLOCK_50, H1L553, H1L793, E1_data_out, H1L591, H1L594, H1_W_valid);


--W1L73 is DE2_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|p1_tri_state_bridge_0_address[10]~209
W1L73 = W1L137 & H1_W_alu_result[10] # !W1L137 & (H1_F_pc[8]);


--H1_W_alu_result[9] is DE2_Board:inst|cpu_0:the_cpu_0|W_alu_result[9]
H1_W_alu_result[9] = AMPP_FUNCTION(CLOCK_50, H1L696, H1_E_shift_rot_result[9], E1_data_out, H1L127, H1_R_ctrl_shift_rot);