library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MBR is
port(
     clk:in std_logic ;
     ACC_in: in std_logic_vector( 15 downto 0);
     memory_in: in std_logic_vector(15 downto 0);
     mul_in: in std_logic_vector(15 downto 0);
     MBR_out: out std_logic_vector(15 downto 0);
     C: in std_logic_vector(31 downto 0)
);
end MBR;
architecture MBR_behave of MBR is
begin
process(clk)
  begin
    if clk'event and clk='1' then
      if C(3)='1' then         --MBR<=memory
        MBR_out<=memory_in;    
      elsif C(18)='1' then
       MBR_out<=ACC_in;
      elsif C(26)='1' then
        MBR_out<=mul_in;
     end if;
    end if;
end process;
end MBR_behave;