library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY MBR IS
	PORT
	(	acc_in,memory_in	  : IN	std_logic_vector(15 downto 0);
        cs			          : IN	std_logic_vector(31 downto 0);
		clk	                  : IN  std_logic;
		mbr_out		          : out std_logic_vector(15 downto 0)
    );
END MBR;

ARCHITECTURE behave OF MBR IS
BEGIN
	PROCESS(clk)
		BEGIN
			IF clk'event and clk='1' THEN
				if cs(15)='1' then  --memory to MBR
					mbr_out<=memory_in;
				elsif cs(16)='1' then  --ACC to MBR
					mbr_out<=acc_in;
				end if;
			END IF;
	END PROCESS;
END behave;