library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;
library lpm;
use lpm.lpm_components.all;
entity ddsc is
   generic( freq_width : integer := 32;
            phase_width : integer := 12;
            adder_width : integer := 32;
            romad_width : integer := 10;
            rom_d_width : integer := 10);
   port( clk      : in std_logic;
freqin : in std_logic_vector (freq_width-1 downto 0);
--phasein : in std_logic_vector(phase_width-1 downto 0);
ddsout : out std_logic_vector(rom_d_width-1 downto 0));
end entity ddsc;
architecture behave of ddsc is
    signal acc    : std_logic_vector(adder_width-1 downto 0);
--    signal phaseadd : std_logic_vector(phase_width-1 downto 0);
    signal romaddr : std_logic_vector(romad_width-1 downto 0);
    signal freqw : std_logic_vector(freq_width-1 downto 0);
    signal phasew : std_logic_vector(phase_width-1 downto 0);
begin
    freqw <= freqin;
    process (clk)
    begin
       if(clk'event and clk = '1') then
--          freqw <= freqin;
--          phasew <= phasein;
          acc <= acc + freqw;
        end if;
     end process;
--   phaseadd <= acc(adder_width-1 downto adder_width-phase_width) + phasew;
   phaseadd <= acc(adder_width-1 downto adder_width-phase_width);
   romaddr <= phaseadd(phase_width-1 downto phase_width-romad_width);
   i_rom : lpm_rom
GENERIC MAP ( LPM_WIDTH => rom_d_width,
              LPM_WIDTHAD => romad_width,
         LPM_ADDRESS_CONTROL => "UNREGISTERED",
              LPM_OUTDATA => "REGISTERED",
                 LPM_FILE => "sin_rom.mif" )
PORT MAP ( outclock => clk,address => romaddr,q => ddsout );
end architecture behave;