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-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 6.1 Build 201 11/27/2006 SJ Full Version"

-- DATE "05/12/2009 15:42:05"

-- 
-- Device: Altera EP2C20Q240C8 Package PQFP240
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cycloneii;
USE IEEE.std_logic_1164.all;
USE cycloneii.cycloneii_components.all;

ENTITY 	ddsc IS
    PORT (
	clk : IN std_logic;
	freqin : IN std_logic_vector(31 DOWNTO 0);
	ddsout : OUT std_logic_vector(9 DOWNTO 0)
	);
END ddsc;

ARCHITECTURE structure OF ddsc IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_freqin : std_logic_vector(31 DOWNTO 0);
SIGNAL ww_ddsout : std_logic_vector(9 DOWNTO 0);
SIGNAL \i_rom|srom|rom_block|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \i_rom|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \i_rom|srom|rom_block|auto_generated|ram_block1a4_PORTAADDR_bus\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \i_rom|srom|rom_block|auto_generated|ram_block1a4_PORTADATAOUT_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \i_rom|srom|rom_block|auto_generated|ram_block1a8_PORTAADDR_bus\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \i_rom|srom|rom_block|auto_generated|ram_block1a8_PORTADATAOUT_bus\ : std_logic_vector(1 DOWNTO 0);
SIGNAL \clk~clkctrl_I_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \acc[3]~156\ : std_logic;
SIGNAL \acc[5]~154\ : std_logic;
SIGNAL \acc[6]~153\ : std_logic;
SIGNAL \acc[8]~151\ : std_logic;
SIGNAL \acc[10]~149\ : std_logic;
SIGNAL \acc[12]~147\ : std_logic;
SIGNAL \acc[19]~140\ : std_logic;
SIGNAL \acc[21]~138\ : std_logic;
SIGNAL \clk~combout\ : std_logic;
SIGNAL \clk~clkctrl\ : std_logic;
SIGNAL \acc[0]~159\ : std_logic;
SIGNAL \acc[0]~160\ : std_logic;
SIGNAL \acc[1]~158\ : std_logic;
SIGNAL \acc[1]~161\ : std_logic;
SIGNAL \acc[2]~157\ : std_logic;
SIGNAL \acc[2]~162\ : std_logic;
SIGNAL \acc[3]~163\ : std_logic;
SIGNAL \acc[4]~155\ : std_logic;
SIGNAL \acc[4]~164\ : std_logic;
SIGNAL \acc[5]~165\ : std_logic;
SIGNAL \acc[6]~166\ : std_logic;
SIGNAL \acc[7]~152\ : std_logic;
SIGNAL \acc[7]~167\ : std_logic;
SIGNAL \acc[8]~168\ : std_logic;
SIGNAL \acc[9]~150\ : std_logic;
SIGNAL \acc[9]~169\ : std_logic;
SIGNAL \acc[10]~170\ : std_logic;
SIGNAL \acc[11]~148\ : std_logic;
SIGNAL \acc[11]~171\ : std_logic;
SIGNAL \acc[12]~172\ : std_logic;
SIGNAL \acc[13]~146\ : std_logic;
SIGNAL \acc[13]~173\ : std_logic;
SIGNAL \acc[14]~145\ : std_logic;
SIGNAL \acc[14]~174\ : std_logic;
SIGNAL \acc[15]~144\ : std_logic;
SIGNAL \acc[15]~175\ : std_logic;
SIGNAL \acc[16]~143\ : std_logic;
SIGNAL \acc[16]~176\ : std_logic;
SIGNAL \acc[17]~142\ : std_logic;
SIGNAL \acc[17]~177\ : std_logic;
SIGNAL \acc[18]~141\ : std_logic;
SIGNAL \acc[18]~178\ : std_logic;
SIGNAL \acc[19]~179\ : std_logic;
SIGNAL \acc[20]~139\ : std_logic;
SIGNAL \acc[20]~180\ : std_logic;
SIGNAL \acc[21]~181\ : std_logic;
SIGNAL \acc[22]~128\ : std_logic;
SIGNAL \acc[22]~182\ : std_logic;
SIGNAL \acc[23]~129\ : std_logic;
SIGNAL \acc[23]~183\ : std_logic;
SIGNAL \acc[24]~130\ : std_logic;
SIGNAL \acc[24]~184\ : std_logic;
SIGNAL \acc[25]~131\ : std_logic;
SIGNAL \acc[25]~185\ : std_logic;
SIGNAL \acc[26]~132\ : std_logic;
SIGNAL \acc[26]~186\ : std_logic;
SIGNAL \acc[27]~133\ : std_logic;
SIGNAL \acc[27]~187\ : std_logic;
SIGNAL \acc[28]~134\ : std_logic;
SIGNAL \acc[28]~188\ : std_logic;
SIGNAL \acc[29]~135\ : std_logic;
SIGNAL \acc[29]~189\ : std_logic;
SIGNAL \acc[30]~136\ : std_logic;
SIGNAL \acc[30]~190\ : std_logic;
SIGNAL \acc[31]~137\ : std_logic;
SIGNAL \i_rom|srom|rom_block|auto_generated|q_a\ : std_logic_vector(9 DOWNTO 0);
SIGNAL acc : std_logic_vector(31 DOWNTO 0);
SIGNAL \freqin~combout\ : std_logic_vector(31 DOWNTO 0);

BEGIN

ww_clk <= clk;
ww_freqin <= freqin;
ddsout <= ww_ddsout;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\i_rom|srom|rom_block|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (acc(31) & acc(30) & acc(29) & acc(28) & acc(27) & acc(26) & acc(25) & acc(24) & acc(23) & acc(22));

\i_rom|srom|rom_block|auto_generated|q_a\(0) <= \i_rom|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus\(0);
\i_rom|srom|rom_block|auto_generated|q_a\(1) <= \i_rom|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus\(1);
\i_rom|srom|rom_block|auto_generated|q_a\(2) <= \i_rom|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus\(2);
\i_rom|srom|rom_block|auto_generated|q_a\(3) <= \i_rom|srom|rom_block|auto_generated|ram_block1a0_PORTADATAOUT_bus\(3);

\i_rom|srom|rom_block|auto_generated|ram_block1a4_PORTAADDR_bus\ <= (acc(31) & acc(30) & acc(29) & acc(28) & acc(27) & acc(26) & acc(25) & acc(24) & acc(23) & acc(22));

\i_rom|srom|rom_block|auto_generated|q_a\(4) <= \i_rom|srom|rom_block|auto_generated|ram_block1a4_PORTADATAOUT_bus\(0);
\i_rom|srom|rom_block|auto_generated|q_a\(5) <= \i_rom|srom|rom_block|auto_generated|ram_block1a4_PORTADATAOUT_bus\(1);
\i_rom|srom|rom_block|auto_generated|q_a\(6) <= \i_rom|srom|rom_block|auto_generated|ram_block1a4_PORTADATAOUT_bus\(2);
\i_rom|srom|rom_block|auto_generated|q_a\(7) <= \i_rom|srom|rom_block|auto_generated|ram_block1a4_PORTADATAOUT_bus\(3);

\i_rom|srom|rom_block|auto_generated|ram_block1a8_PORTAADDR_bus\ <= (acc(31) & acc(30) & acc(29) & acc(28) & acc(27) & acc(26) & acc(25) & acc(24) & acc(23) & acc(22));

\i_rom|srom|rom_block|auto_generated|q_a\(8) <= \i_rom|srom|rom_block|auto_generated|ram_block1a8_PORTADATAOUT_bus\(0);
\i_rom|srom|rom_block|auto_generated|q_a\(9) <= \i_rom|srom|rom_block|auto_generated|ram_block1a8_PORTADATAOUT_bus\(1);

\clk~clkctrl_I_INCLK_bus\ <= (gnd & gnd & gnd & \clk~combout\);

\acc[21]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \acc[21]~138\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => acc(21));

\freqin[20]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_freqin(20),
	combout => \freqin~combout\(20));

\acc[19]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \acc[19]~140\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => acc(19));

\freqin[18]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_freqin(18),
	combout => \freqin~combout\(18));

\freqin[17]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_freqin(17),
	combout => \freqin~combout\(17));

\freqin[16]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_freqin(16),
	combout => \freqin~combout\(16));

\freqin[15]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_freqin(15),
	combout => \freqin~combout\(15));

\freqin[14]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_freqin(14),
	combout => \freqin~combout\(14));

\freqin[13]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_freqin(13),
	combout => \freqin~combout\(13));

\acc[12]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \acc[12]~147\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => acc(12));

\freqin[11]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_freqin(11),
	combout => \freqin~combout\(11));

\acc[10]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \acc[10]~149\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => acc(10));

\freqin[9]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",
	output_power_up => "low",
	output_register_mode => "none",
	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_freqin(9),
	combout => \freqin~combout\(9));

\acc[8]~I\ : cycloneii_lcell_ff
PORT MAP (
	clk => \clk~clkctrl\,
	datain => \acc[8]~151\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => acc(8));

\freqin[7]~I\ : cycloneii_io
-- pragma translate_off
GENERIC MAP (
	input_async_reset => "none",
	input_power_up => "low",
	input_register_mode => "none",
	input_sync_reset => "none",
	oe_async_reset => "none",
	oe_power_up => "low",
	oe_register_mode => "none",
	oe_sync_reset => "none",
	operation_mode => "input",
	output_async_reset => "none",

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亚洲欧美第一页_禁久久精品乱码_粉嫩av一区二区三区免费野_久草精品视频
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