|ddsc
clk => LPM_ROM:i_rom.OUTCLOCK
clk => acc[0].CLK
clk => acc[1].CLK
clk => acc[2].CLK
clk => acc[3].CLK
clk => acc[4].CLK
clk => acc[5].CLK
clk => acc[6].CLK
clk => acc[7].CLK
clk => acc[8].CLK
clk => acc[9].CLK
clk => acc[10].CLK
clk => acc[11].CLK
clk => acc[12].CLK
clk => acc[13].CLK
clk => acc[14].CLK
clk => acc[15].CLK
clk => acc[16].CLK
clk => acc[17].CLK
clk => acc[18].CLK
clk => acc[19].CLK
clk => acc[20].CLK
clk => acc[21].CLK
clk => acc[22].CLK
clk => acc[23].CLK
clk => acc[24].CLK
clk => acc[25].CLK
clk => acc[26].CLK
clk => acc[27].CLK
clk => acc[28].CLK
clk => acc[29].CLK
clk => acc[30].CLK
clk => acc[31].CLK
freqin[0] => Add0.IN64
freqin[1] => Add0.IN63
freqin[2] => Add0.IN62
freqin[3] => Add0.IN61
freqin[4] => Add0.IN60
freqin[5] => Add0.IN59
freqin[6] => Add0.IN58
freqin[7] => Add0.IN57
freqin[8] => Add0.IN56
freqin[9] => Add0.IN55
freqin[10] => Add0.IN54
freqin[11] => Add0.IN53
freqin[12] => Add0.IN52
freqin[13] => Add0.IN51
freqin[14] => Add0.IN50
freqin[15] => Add0.IN49
freqin[16] => Add0.IN48
freqin[17] => Add0.IN47
freqin[18] => Add0.IN46
freqin[19] => Add0.IN45
freqin[20] => Add0.IN44
freqin[21] => Add0.IN43
freqin[22] => Add0.IN42
freqin[23] => Add0.IN41
freqin[24] => Add0.IN40
freqin[25] => Add0.IN39
freqin[26] => Add0.IN38
freqin[27] => Add0.IN37
freqin[28] => Add0.IN36
freqin[29] => Add0.IN35
freqin[30] => Add0.IN34
freqin[31] => Add0.IN33
ddsout[0] <= LPM_ROM:i_rom.Q[0]
ddsout[1] <= LPM_ROM:i_rom.Q[1]
ddsout[2] <= LPM_ROM:i_rom.Q[2]
ddsout[3] <= LPM_ROM:i_rom.Q[3]
ddsout[4] <= LPM_ROM:i_rom.Q[4]
ddsout[5] <= LPM_ROM:i_rom.Q[5]
ddsout[6] <= LPM_ROM:i_rom.Q[6]
ddsout[7] <= LPM_ROM:i_rom.Q[7]
ddsout[8] <= LPM_ROM:i_rom.Q[8]
ddsout[9] <= LPM_ROM:i_rom.Q[9]


|ddsc|LPM_ROM:i_rom
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
address[8] => altrom:srom.address[8]
address[9] => altrom:srom.address[9]
inclock => ~NO_FANOUT~
outclock => altrom:srom.clocko
memenab => otri[9].OE
memenab => otri[8].OE
memenab => otri[7].OE
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= otri[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= otri[9].DB_MAX_OUTPUT_PORT_TYPE


|ddsc|LPM_ROM:i_rom|altrom:srom
address[0] => altsyncram:rom_block.address_a[0]
address[1] => altsyncram:rom_block.address_a[1]
address[2] => altsyncram:rom_block.address_a[2]
address[3] => altsyncram:rom_block.address_a[3]
address[4] => altsyncram:rom_block.address_a[4]
address[5] => altsyncram:rom_block.address_a[5]
address[6] => altsyncram:rom_block.address_a[6]
address[7] => altsyncram:rom_block.address_a[7]
address[8] => altsyncram:rom_block.address_a[8]
address[9] => altsyncram:rom_block.address_a[9]
clocki => ~NO_FANOUT~
clocko => altsyncram:rom_block.clock0
q[0] <= altsyncram:rom_block.q_a[0]
q[1] <= altsyncram:rom_block.q_a[1]
q[2] <= altsyncram:rom_block.q_a[2]
q[3] <= altsyncram:rom_block.q_a[3]
q[4] <= altsyncram:rom_block.q_a[4]
q[5] <= altsyncram:rom_block.q_a[5]
q[6] <= altsyncram:rom_block.q_a[6]
q[7] <= altsyncram:rom_block.q_a[7]
q[8] <= altsyncram:rom_block.q_a[8]
q[9] <= altsyncram:rom_block.q_a[9]


|ddsc|LPM_ROM:i_rom|altrom:srom|altsyncram:rom_block
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_hb01:auto_generated.address_a[0]
address_a[1] => altsyncram_hb01:auto_generated.address_a[1]
address_a[2] => altsyncram_hb01:auto_generated.address_a[2]
address_a[3] => altsyncram_hb01:auto_generated.address_a[3]
address_a[4] => altsyncram_hb01:auto_generated.address_a[4]
address_a[5] => altsyncram_hb01:auto_generated.address_a[5]
address_a[6] => altsyncram_hb01:auto_generated.address_a[6]
address_a[7] => altsyncram_hb01:auto_generated.address_a[7]
address_a[8] => altsyncram_hb01:auto_generated.address_a[8]
address_a[9] => altsyncram_hb01:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_hb01:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_hb01:auto_generated.q_a[0]
q_a[1] <= altsyncram_hb01:auto_generated.q_a[1]
q_a[2] <= altsyncram_hb01:auto_generated.q_a[2]
q_a[3] <= altsyncram_hb01:auto_generated.q_a[3]
q_a[4] <= altsyncram_hb01:auto_generated.q_a[4]
q_a[5] <= altsyncram_hb01:auto_generated.q_a[5]
q_a[6] <= altsyncram_hb01:auto_generated.q_a[6]
q_a[7] <= altsyncram_hb01:auto_generated.q_a[7]
q_a[8] <= altsyncram_hb01:auto_generated.q_a[8]
q_a[9] <= altsyncram_hb01:auto_generated.q_a[9]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|ddsc|LPM_ROM:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_hb01:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT