{ "Info" "ITDB_FULL_TCO_RESULT" "clk ddsout\[6\] lpm_rom:i_rom\|altrom:srom\|altsyncram:rom_block\|altsyncram_hb01:auto_generated\|ram_block1a4~porta_address_reg0 14.226 ns memory " "Info: tco from clock \"clk\" to destination pin \"ddsout\[6\]\" through memory \"lpm_rom:i_rom\|altrom:srom\|altsyncram:rom_block\|altsyncram_hb01:auto_generated\|ram_block1a4~porta_address_reg0\" is 14.226 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.253 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 3.253 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.170 ns) 1.170 ns clk 1 CLK PIN_34 1 " "Info: 1: + IC(0.000 ns) + CELL(1.170 ns) = 1.170 ns; Loc. = PIN_34; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ddsc.vhd" "" { Text "D:/畢業設計/dds/ddsc.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.000 ns) 1.427 ns clk~clkctrl 2 COMB CLKCTRL_G3 62 " "Info: 2: + IC(0.257 ns) + CELL(0.000 ns) = 1.427 ns; Loc. = CLKCTRL_G3; Fanout = 62; COMB Node = 'clk~clkctrl'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.257 ns" { clk clk~clkctrl } "NODE_NAME" } } { "ddsc.vhd" "" { Text "D:/畢業設計/dds/ddsc.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.991 ns) + CELL(0.835 ns) 3.253 ns lpm_rom:i_rom\|altrom:srom\|altsyncram:rom_block\|altsyncram_hb01:auto_generated\|ram_block1a4~porta_address_reg0 3 MEM M4K_X17_Y18 4 " "Info: 3: + IC(0.991 ns) + CELL(0.835 ns) = 3.253 ns; Loc. = M4K_X17_Y18; Fanout = 4; MEM Node = 'lpm_rom:i_rom\|altrom:srom\|altsyncram:rom_block\|altsyncram_hb01:auto_generated\|ram_block1a4~porta_address_reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.826 ns" { clk~clkctrl lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_hb01:auto_generated|ram_block1a4~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_hb01.tdf" "" { Text "D:/畢業設計/dds/db/altsyncram_hb01.tdf" 123 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.005 ns ( 61.64 % ) " "Info: Total cell delay = 2.005 ns ( 61.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.248 ns ( 38.36 % ) " "Info: Total interconnect delay = 1.248 ns ( 38.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.253 ns" { clk clk~clkctrl lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_hb01:auto_generated|ram_block1a4~porta_address_reg0 } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.253 ns" { clk clk~combout clk~clkctrl lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_hb01:auto_generated|ram_block1a4~porta_address_reg0 } { 0.000ns 0.000ns 0.257ns 0.991ns } { 0.000ns 1.170ns 0.000ns 0.835ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_hb01.tdf" "" { Text "D:/畢業設計/dds/db/altsyncram_hb01.tdf" 123 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.713 ns + Longest memory pin " "Info: + Longest memory to pin delay is 10.713 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_rom:i_rom\|altrom:srom\|altsyncram:rom_block\|altsyncram_hb01:auto_generated\|ram_block1a4~porta_address_reg0 1 MEM M4K_X17_Y18 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y18; Fanout = 4; MEM Node = 'lpm_rom:i_rom\|altrom:srom\|altsyncram:rom_block\|altsyncram_hb01:auto_generated\|ram_block1a4~porta_address_reg0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_hb01:auto_generated|ram_block1a4~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_hb01.tdf" "" { Text "D:/畢業設計/dds/db/altsyncram_hb01.tdf" 123 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.761 ns) 3.761 ns lpm_rom:i_rom\|altrom:srom\|altsyncram:rom_block\|altsyncram_hb01:auto_generated\|q_a\[6\] 2 MEM M4K_X17_Y18 1 " "Info: 2: + IC(0.000 ns) + CELL(3.761 ns) = 3.761 ns; Loc. = M4K_X17_Y18; Fanout = 1; MEM Node = 'lpm_rom:i_rom\|altrom:srom\|altsyncram:rom_block\|altsyncram_hb01:auto_generated\|q_a\[6\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.761 ns" { lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_hb01:auto_generated|ram_block1a4~porta_address_reg0 lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_hb01:auto_generated|q_a[6] } "NODE_NAME" } } { "db/altsyncram_hb01.tdf" "" { Text "D:/畢業設計/dds/db/altsyncram_hb01.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.856 ns) + CELL(3.096 ns) 10.713 ns ddsout\[6\] 3 PIN PIN_168 0 " "Info: 3: + IC(3.856 ns) + CELL(3.096 ns) = 10.713 ns; Loc. = PIN_168; Fanout = 0; PIN Node = 'ddsout\[6\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.952 ns" { lpm_rom:i_rom|altrom:srom|altsyncram:rom_block|altsyncram_hb01:auto_generated|q_a[6] ddsout[6] } "NODE_NAME" } } { "ddsc.vhd" "" { Text "D:/畢業設計/dds/ddsc.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.857 ns ( 64.01 % ) " "Info: Total cell delay = 6.857 ns ( 64.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.856 ns ( 35.99 % ) " "Info: Total interconnect delay = 3.856 ns ( 35.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  }