+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C20Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                  ;
+-----------------------------------------+-----------------------------------------------------+---------+---------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From    ; To                                                                                                            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------+---------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 209.16 MHz ( period = 4.781 ns )                    ; acc[0]  ; acc[31]                                                                                                       ; clk        ; clk      ; None                        ; None                      ; 4.521 ns                ;
; N/A                                     ; 212.81 MHz ( period = 4.699 ns )                    ; acc[1]  ; acc[31]                                                                                                       ; clk        ; clk      ; None                        ; None                      ; 4.439 ns                ;
; N/A                                     ; 212.99 MHz ( period = 4.695 ns )                    ; acc[0]  ; acc[30]                                                                                                       ; clk        ; clk      ; None                        ; None                      ; 4.435 ns                ;
; N/A                                     ; 216.73 MHz ( period = 4.614 ns )                    ; acc[2]  ; acc[31]                                                                                                       ; clk        ; clk      ; None                        ; None                      ; 4.354 ns                ;
; N/A                                     ; 216.78 MHz ( period = 4.613 ns )                    ; acc[1]  ; acc[30]                                                                                                       ; clk        ; clk      ; None                        ; None                      ; 4.353 ns                ;
; N/A                                     ; 216.97 MHz ( period = 4.609 ns )                    ; acc[0]  ; acc[29]                                                                                                       ; clk        ; clk      ; None                        ; None                      ; 4.349 ns                ;
; N/A                                     ; 218.44 MHz ( period = 4.578 ns )                    ; acc[3]  ; acc[31]                                                                                                       ; clk        ; clk      ; None                        ; None                      ; 4.318 ns                ;
; N/A                                     ; 220.85 MHz ( period = 4.528 ns )                    ; acc[2]  ; acc[30]                                                                                                       ; clk        ; clk      ; None                        ; None                      ; 4.268 ns                ;
; N/A                                     ; 220.90 MHz ( period = 4.527 ns )                    ; acc[1]  ; acc[29]                                                                                                       ; clk        ; clk      ; None                        ; None                      ; 4.267 ns                ;
; N/A                                     ; 221.09 MHz ( period = 4.523 ns )                    ; acc[0]  ; acc[28]                                                                                                       ; clk        ; clk      ; None                        ; None                      ; 4.263 ns                ;
; N/A                                     ; 222.62 MHz ( period = 4.492 ns )                    ; acc[3]  ; acc[30]                                                                                                       ; clk        ; clk      ; None                        ; None                      ; 4.232 ns                ;
; N/A                                     ; 225.07 MHz ( period = 4.443 ns )                    ; acc[4]  ; acc[31]                                                                                                       ; clk        ; clk      ; None                        ; None                      ; 4.183 ns                ;