<!--
This XML file (created on Fri Mar 21 17:45:09 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<host_id>000cf1496c62</host_id>
	<nic_id>000cf1496c62</nic_id>
	<cdrive_id>38441af0</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_tan.exe</module>
	<edition>Web Edition</edition>
	<compilation_end_time>Fri Mar 21 17:45:09 2008</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">1399</cpu_freq>
	</cpu>
	<ram units="MB">751</ram>
</machine>
<top_file>E:/EDA_QuartusII/chap6_vhdl2/counter_6.1/cnt42</top_file>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off cnt42 -c cnt42</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<warning>Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings</info>
	<info>Info: Elapsed time: 00:00:01</info>
	<info>Info: Processing ended: Fri Mar 21 17:45:09 2008</info>
	<info>Info: tco from clock &quot;CLK&quot; to destination pin &quot;Q[3]&quot; through register &quot;lpm_counter:Q1_rtl_0|dffs[3]&quot; is 2.800 ns</info>
	<info>Info: + Longest register to pin delay is 0.200 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>CLK</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>2.800 ns</actual>
	</nonclk>
	<clk>
		<name>CLK</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>175.44 MHz ( period = 5.700 ns )</actual>
	</clk>
</performance>
<compile_id>C548F2CD</compile_id>
</talkback>