?? cnt42.tan.rpt
字號:
Timing Analyzer report for cnt42
Fri Mar 21 17:45:09 2008
Version 5.1 Build 176 10/26/2005 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'CLK'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+------------------------------+------------------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+------------------------------+------------------------------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 2.800 ns ; lpm_counter:Q1_rtl_0|dffs[0] ; Q[0] ; CLK ; -- ; 0 ;
; Clock Setup: 'CLK' ; N/A ; None ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:Q1_rtl_0|dffs[0] ; lpm_counter:Q1_rtl_0|dffs[0] ; CLK ; CLK ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+------------------------------+------------------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM7032SLC44-5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Minimum tpd to report ; 0 ns ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; Off ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK' ;
+-------+----------------------------------+------------------------------+------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+------------------------------+------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:Q1_rtl_0|dffs[0] ; lpm_counter:Q1_rtl_0|dffs[3] ; CLK ; CLK ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:Q1_rtl_0|dffs[1] ; lpm_counter:Q1_rtl_0|dffs[3] ; CLK ; CLK ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:Q1_rtl_0|dffs[2] ; lpm_counter:Q1_rtl_0|dffs[3] ; CLK ; CLK ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:Q1_rtl_0|dffs[3] ; lpm_counter:Q1_rtl_0|dffs[3] ; CLK ; CLK ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:Q1_rtl_0|dffs[0] ; lpm_counter:Q1_rtl_0|dffs[2] ; CLK ; CLK ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:Q1_rtl_0|dffs[1] ; lpm_counter:Q1_rtl_0|dffs[2] ; CLK ; CLK ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:Q1_rtl_0|dffs[2] ; lpm_counter:Q1_rtl_0|dffs[2] ; CLK ; CLK ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:Q1_rtl_0|dffs[0] ; lpm_counter:Q1_rtl_0|dffs[1] ; CLK ; CLK ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:Q1_rtl_0|dffs[1] ; lpm_counter:Q1_rtl_0|dffs[1] ; CLK ; CLK ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:Q1_rtl_0|dffs[0] ; lpm_counter:Q1_rtl_0|dffs[0] ; CLK ; CLK ; None ; None ; 3.600 ns ;
+-------+----------------------------------+------------------------------+------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+------------------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------------------------------+------+------------+
; N/A ; None ; 2.800 ns ; lpm_counter:Q1_rtl_0|dffs[3] ; Q[3] ; CLK ;
; N/A ; None ; 2.800 ns ; lpm_counter:Q1_rtl_0|dffs[2] ; Q[2] ; CLK ;
; N/A ; None ; 2.800 ns ; lpm_counter:Q1_rtl_0|dffs[1] ; Q[1] ; CLK ;
; N/A ; None ; 2.800 ns ; lpm_counter:Q1_rtl_0|dffs[0] ; Q[0] ; CLK ;
+-------+--------------+------------+------------------------------+------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
Info: Processing started: Fri Mar 21 17:45:08 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cnt42 -c cnt42
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 175.44 MHz between source register "lpm_counter:Q1_rtl_0|dffs[0]" and destination register "lpm_counter:Q1_rtl_0|dffs[3]" (period= 5.7 ns)
Info: + Longest register to register delay is 3.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'lpm_counter:Q1_rtl_0|dffs[0]'
Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:Q1_rtl_0|dffs[3]'
Info: Total cell delay = 2.600 ns ( 72.22 % )
Info: Total interconnect delay = 1.000 ns ( 27.78 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "CLK" to destination register is 1.300 ns
Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'
Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:Q1_rtl_0|dffs[3]'
Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: - Longest clock path from clock "CLK" to source register is 1.300 ns
Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'
Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 5; REG Node = 'lpm_counter:Q1_rtl_0|dffs[0]'
Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.300 ns
Info: + Micro setup delay of destination is 0.800 ns
Info: tco from clock "CLK" to destination pin "Q[3]" through register "lpm_counter:Q1_rtl_0|dffs[3]" is 2.800 ns
Info: + Longest clock path from clock "CLK" to source register is 1.300 ns
Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'CLK'
Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:Q1_rtl_0|dffs[3]'
Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.300 ns
Info: + Longest register to pin delay is 0.200 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:Q1_rtl_0|dffs[3]'
Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'Q[3]'
Info: Total cell delay = 0.200 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
Info: Processing ended: Fri Mar 21 17:45:09 2008
Info: Elapsed time: 00:00:01
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