library verilog;use verilog.vl_types.all;entity router_dft is    port(        reqin_east      : in     vl_logic;        din_east        : in     vl_logic_vector(33 downto 0);        ackout_east     : out    vl_logic;        reqin_south     : in     vl_logic;        din_south       : in     vl_logic_vector(33 downto 0);        ackout_south    : out    vl_logic;        reqin_west      : in     vl_logic;        din_west        : in     vl_logic_vector(33 downto 0);        ackout_west     : out    vl_logic;        reqin_north     : in     vl_logic;        din_north       : in     vl_logic_vector(33 downto 0);        ackout_north    : out    vl_logic;        reqin_core      : in     vl_logic;        din_core        : in     vl_logic_vector(33 downto 0);        ackout_core     : out    vl_logic;        reqout_east     : out    vl_logic;        dout_east       : out    vl_logic_vector(33 downto 0);        ackin_east      : in     vl_logic;        reqout_south    : out    vl_logic;        dout_south      : out    vl_logic_vector(33 downto 0);        ackin_south     : in     vl_logic;        reqout_west     : out    vl_logic;        dout_west       : out    vl_logic_vector(33 downto 0);        ackin_west      : in     vl_logic;        reqout_north    : out    vl_logic;        dout_north      : out    vl_logic_vector(33 downto 0);        ackin_north     : in     vl_logic;        reqout_core     : out    vl_logic;        dout_core       : out    vl_logic_vector(33 downto 0);        ackin_core      : in     vl_logic;        clk             : in     vl_logic;        rst             : in     vl_logic;        ten             : in     vl_logic    );end router_dft;