?? _primary.vhd
字號(hào):
library verilog;use verilog.vl_types.all;entity SK is port( rst : in vl_logic; ack_in : in vl_logic; din_3 : in vl_logic_vector(33 downto 0); din : in vl_logic_vector(33 downto 0); dout : out vl_logic_vector(33 downto 0); did : out vl_logic_vector(2 downto 0); req_c : out vl_logic );end SK;
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