library verilog;use verilog.vl_types.all;entity inctl is    generic(        WAIT_DATA       : integer := 0;        WAIT_REQ        : integer := 1;        TEST            : integer := 3;        PRE_SEND        : integer := 0;        WAIT_ACK        : integer := 1;        WAIT_ACK_DOWN   : integer := 2    );    port(        clk             : in     vl_logic;        rst             : in     vl_logic;        req_in          : in     vl_logic;        din             : in     vl_logic_vector(33 downto 0);        ack_in          : in     vl_logic;        ack_out         : out    vl_logic;        du_3            : out    vl_logic_vector(33 downto 0);        dout            : out    vl_logic_vector(33 downto 0);        req_out         : out    vl_logic;        ten             : in     vl_logic    );end inctl;