module testbench();    reg clk, rst;        reg send_r;    wire send;    wire req_out, ack_in, reqout_router, ack_out;    wire [33:0] dout;        assign send = send_r;    always #5 clk = ~clk;          sender s1(.clk(clk), .send(send), .req_out(req_out), .dout(dout), .ack_in(ack_in));//east->south    receiver r1(.clk(clk), .req_in(reqout_router), .ack_out(ack_out));        router r(.clk(clk), .rst(rst),             .reqin_east(req_out), .din_east(dout), .ackout_east(ack_in),             .reqin_south(0),.din_south(0),             .reqin_west(0), .din_west(0),             .reqin_north(0), .din_north(0),             .reqin_core(0), .din_core(0),             .ackin_east(0),             .reqout_south(reqout_router), .ackin_south(ack_out),             .ackin_west(0),             .ackin_north(0),             .ackin_core(0)             );        initial    begin        clk = 0;        rst = 1;        send_r = 1;        #15;        rst = 0;    end    endmodule