?? 65_conditioner.vhd
字號:
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
ENTITY air_conditioner IS
PORT(clk : IN Std_ULogic;
temp_high :IN Std_ULogic;
temp_low : IN Std_ULogic;
heat : OUT Std_ULogic;
cool : OUT Std_ULogic);
END air_conditioner;
ARCHITECTURE style_b OF air_conditioner IS
TYPE state_type IS (just_right,too_cold,too_hot);
ATTRIBUTE sequential_encoding : String;
ATTRIBUTE sequential_encoding OF state_type :TYPE IS "00 01 10";
SIGNAL stvar: state_type;
ATTRIBUTE state_vector : String;
ATTRIBUTE state_vector OF style_b:ARCHITECTURE IS "stvar";
BEGIN
controller1 : PROCESS
BEGIN
WAIT UNTIL clk='1'; --revised by dls
IF (temp_low='1') THEN stvar<=too_cold;
ELSIF (temp_high='1') THEN stvar<=too_hot;
ELSE stvar<=just_right;
END IF;
CASE stvar IS
WHEN just_right=>heat<='0';cool<='0';
WHEN too_cold=>heat<='1';cool<='0';
WHEN too_hot=>heat<='0';cool<='1';
END CASE;
END PROCESS controller1;
END style_b;
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