vhdl "\t\t\t\tcarry <= new_phase(num_bits - 1);\n";    vhdl "\t\t\t\tif (carry = '1') then\n";    vhdl "\t\t\t\t\tmsb <= not msb;\t-- toggle msb\n";    vhdl "\t\t\t\tend if;\n";    vhdl "\t\t\t\toutput_pulse <= msb and carry;\n";    #vhdl "\t\t\t\t-- decode counter\n";    vhdl "\t\t\t\td_carry <= carry;\n";    vhdl "\t\t\t\td_msb_1 <= msb and not (d_carry and late);\n";    vhdl "\t\t\t\tif (carry = '1') then\n";    vhdl "\t\t\t\t\tlate <= phase_diff(num_bits);\n";    vhdl "\t\t\t\tend if;\n";    vhdl "\t\t\tend if;\n";    vhdl "\t\tend if;\n";    vhdl "\tend process phase_accumulator;\n";    vhdl "\n";    vhdl "\tphase_diff <= (phase(num_bits - 2 downto 0) & '0') - ('0' & c);\n";    vhdl "\n";    vhdl "\toutput_50 <= d_msb_1 or d_msb_2_neg;\n";    vhdl "\n";    vhdl "\tneg_edge : process (async_reset, clock)\n";    vhdl "\tbegin\n";    vhdl "\t\tif (async_reset = '1') then\n";    vhdl "\t\t\td_msb_2_neg <= '0';\n";    vhdl "\t\telsif (falling_edge(clock)) then\n";    vhdl "\t\t\tif (clock_enable = '1') then\n";    vhdl "\t\t\t\td_msb_2_neg <= msb xor (d_carry and not (not late and not msb));\n";    vhdl "\t\t\tend if;\n";    vhdl "\t\tend if;\n";    vhdl "\tend process neg_edge;\n";    vhdl "\n";    vhdl "\tassert c(num_bits - 1) = '0' severity failure; \n";    vhdl "\n";    vhdl "end generate gen_other_phase_accumulator;\n";    vhdl "\n";}verilog "/** this section not yet implemented in the Verilog version */\n\n";# write prescaler processcomment_line;comment " Prescaler.  Divides by either $n or " . ($n+1) . "\n";comment " depending on whether the signal \"modulus_control\" is '0' or '1'.\n";comment " Note: the \"terminal count\" is fixed, and the load value is\n";comment " varied, to give smaller, faster logic (?)\n";comment_line;vhdl "gen_prescaler : if not use_phase_accumulator generate\n";vhdl "\tprescaler : process (async_reset, clock)\n";vhdl "\tbegin\n";vhdl "\t\tif (async_reset = '1') then\n";vhdl "\t\t\tprescaler_count  <= 0;\n";vhdl "\t\t\tprescaler_out    <= '0';\n" if ($n > 1);#vhdl "--" if (not $gen_50_percent_output);vhdl "\t\t\tprescaler_out_50 <= '0';\n";vhdl "\t\telsif (rising_edge(clock)) then\n";vhdl "\t\t\tif (clock_enable = '1') then\n";vhdl "\t\t\t\t-- manage counter\n";vhdl "\t\t\t\tif (prescaler_count < n) then\n";vhdl "\t\t\t\t\tprescaler_count <= prescaler_count + 1;\n";vhdl "\t\t\t\telse\n";vhdl "\t\t\t\t\tif (modulus_control = '0') then\n";vhdl "\t\t\t\t\t\tprescaler_count <= 1;\n";vhdl "\t\t\t\t\telse\n";vhdl "\t\t\t\t\t\tprescaler_count <= 0;\n";vhdl "\t\t\t\t\tend if;\n";vhdl "\t\t\t\tend if;\n";if ($n > 1) {    # only need to decode if there are more than 2 states (i.e. > 1 ff)    vhdl "\t\t\t\t-- decode counter\n";    vhdl "\t\t\t\tif (prescaler_count < n) then\n";    vhdl "\t\t\t\t\tprescaler_out <= '0';\n";    vhdl "\t\t\t\telse\n";    vhdl "\t\t\t\t\tprescaler_out <= '1';\n";    vhdl "\t\t\t\tend if;\n";}vhdl "\t\t\t\tif (prescaler_count <= n/2) then\n";#vhdl "--" if (not $gen_50_percent_output);vhdl "\t\t\t\t\tprescaler_out_50 <= '0';\n";vhdl "\t\t\t\telse\n";#vhdl "--" if (not $gen_50_percent_output);vhdl "\t\t\t\t\tprescaler_out_50 <= '1';\n";vhdl "\t\t\t\tend if;\n";vhdl "\t\t\tend if;\n";vhdl "\t\tend if;\n";vhdl "\tend process prescaler;\n";vhdl "\n";if ($n <= 1) {    vhdl "\tprescaler_out <= '0' when prescaler_count = 0 else '1';\n";}vhdl "\toutput_pulse <= prescaler_out;\n";vhdl "\n";vhdl "end generate gen_prescaler;\n";vhdl "\n";verilog "\talways @(posedge async_reset or posedge clock ) begin : prescaler\n";verilog "\t\tif (async_reset)\n";verilog "\t\t\tbegin\n";verilog "\t\t\t\tprescaler_count  <= 0;\n";verilog "\t\t\t\tprescaler_out    <= 0;\n" if ($n > 1);#verilog "//" if (not $gen_50_percent_output);verilog "\t\t\t\tprescaler_out_50 <= 0;\n";verilog "\t\t\tend\n";verilog "\t\telse\n";verilog "\t\t\tbegin\n";verilog "\t\t\t\tif (clock_enable)\n";verilog "\t\t\t\t\tbegin\n";verilog "\t\t\t\t\t\t// manage counter\n";verilog "\t\t\t\t\t\tif (prescaler_count < n)\n";#verilog "\t\t\t\t\t\t\tbegin\n";verilog "\t\t\t\t\t\t\tprescaler_count <= prescaler_count + 1;\n";#verilog "\t\t\t\t\t\t\tend\n";verilog "\t\t\t\t\t\telse\n";#verilog "\t\t\t\t\t\t\tbegin\n";verilog "\t\t\t\t\t\t\tprescaler_count <= modulus_control ? 0 : 1;\n";#verilog "\t\t\t\t\t\t\t\tif (!modulus_control)\n";#verilog "\t\t\t\t\t\t\t\t\tbegin\n";#verilog "\t\t\t\t\t\t\t\t\t\tprescaler_count <= 1;\n";#verilog "\t\t\t\t\t\t\t\t\tend\n";#verilog "\t\t\t\t\t\t\t\telse\n";#verilog "\t\t\t\t\t\t\t\t\tbegin\n";#verilog "\t\t\t\t\t\t\t\t\t\tprescaler_count <= 0;\n";#verilog "\t\t\t\t\t\t\t\t\tend\n";#verilog "\t\t\t\t\t\t\t\tend\n";if ($n > 1) {    # only need to decode if there are more than 2 states (i.e. > 1 ff)    verilog "\t\t\t\t\t\t// decode counter\n";    verilog "\t\t\t\t\t\tprescaler_out <= (prescaler_count < n) ? 0 : 1;\n";    #verilog "\t\t\t\t\t\tif (prescaler_count < n) begin\n";    #verilog "\t\t\t\t\t\t\tprescaler_out <= 0;\n";    #verilog "\t\t\t\t\t\tend else begin\n";    #verilog "\t\t\t\t\t\t\tprescaler_out <= 1;\n";    #verilog "\t\t\t\t\t\tend\n";}verilog "\t\t\t\t\t\t// make 50% duty cycle output\n";verilog "\t\t\t\t\t\tprescaler_out_50 <= (prescaler_count <= n/2) ? 0 : 1;\n";#verilog "\t\t\t\t\t\tif (prescaler_count <= n/2) begin\n";##verilog "//" if (not $gen_50_percent_output);#verilog "\t\t\t\t\t\t\tprescaler_out_50 <= 0;\n";#verilog "\t\t\t\t\t\tend else begin\n";##verilog "//" if (not $gen_50_percent_output);#verilog "\t\t\t\t\t\t\tprescaler_out_50 <= 1;\n";#verilog "\t\t\t\t\t\tend\n";verilog "\t\t\t\t\tend\n";verilog "\t\t\tend\n";verilog "\t\tend\n";verilog "\n";if ($n <= 1) {    verilog "\tassign prescaler_out = (prescaler_count ? 1 : 0);\n";}verilog "\tassign output_pulse = prescaler_out;\n";verilog "\n";if ($gen_50_percent_output) {    # write duty cycle correction process    comment_line;    comment " Duty cycle improvement using falling edge flip flop.\n";    comment_line;    vhdl "duty_cycle_improver : if improve_duty_cycle and not use_phase_accumulator generate\n";    vhdl "\timprover : process (async_reset, clock)\n";    vhdl "\tbegin\n";    vhdl "\t\tif (async_reset = '1') then\n";    vhdl "\t\t\tduty_correction <= '0';\n";    vhdl "\t\telsif (falling_edge(clock)) then\n";    vhdl "\t\t\tif (clock_enable = '1') then\n";    vhdl "\t\t\t\tduty_correction <= prescaler_out_50 or modulus_control;\n" if (($n & 1) == 1);    vhdl "\t\t\t\tduty_correction <= prescaler_out_50 and modulus_control;\n" if (($n & 1) == 0);    vhdl "\t\t\tend if;\n";    vhdl "\t\tend if;\n";    vhdl "\tend process improver;\n";    vhdl "\n";    vhdl "\toutput_50 <= duty_correction and prescaler_out_50;\n" if (($n & 1) == 1);    vhdl "\toutput_50 <= duty_correction or prescaler_out_50;\n" if (($n & 1) == 0);    vhdl "\n";    vhdl "end generate duty_cycle_improver;\n";    vhdl "\n";    vhdl "no_duty_cycle_improver : if not improve_duty_cycle and not use_phase_accumulator generate\n";    vhdl "\toutput_50 <= prescaler_out_50;\n";    vhdl "end generate no_duty_cycle_improver;\n";    vhdl "\n";    verilog "/** this section not yet implemented in the Verilog version */\n\n";    verilog "\n";    verilog "\tassign output_50 = prescaler_out_50;\n";    verilog "\n";}# write controller processcomment_line;comment " Controller.\n";comment " Wobbles the signal \"modulus_control\" to cause the prescaler\n";comment " to divide by the correct ratio (in the long term).\n";comment " Modulus_control must be '0' for $a counts of prescaler_out,\n";comment " and '1' for $b counts (out of a total of " . ($a + $b) . " counts).\n";comment " The simple way to do this is to just have modulus_control '0' for\n";comment " all $a counts, then '1' for $b counts, but this may result in severe jitter.\n";comment " The jitter can be reduced (at some hardware cost) by interleaving\n";comment " the '0' and '1' counts.\n";comment " This behaviour can be controlled by the generic parameter \"minimum_jitter\".\n";comment " Note that there are many hardware / jitter tradeoffs.\n";comment " Best results may require human intervention!\n";comment_line;# high jitter controllervhdl "high_jitter_controller : if not minimum_jitter and not use_phase_accumulator and not use_recursive_controller generate\n";vhdl "\tcontroller : process (async_reset, clock)\n";vhdl "\tbegin\n";vhdl "\t\tif (async_reset = '1') then\n";vhdl "\t\t\tmodulus_control <= '0';\n";vhdl "\t\t\tcontroller_count <= 0;\n";vhdl "\t\telsif (rising_edge(clock)) then\n";vhdl "\t\t\tif (clock_enable = '1') then\n";vhdl "\t\t\t\tif (prescaler_out = '1') then\n";vhdl "\t\t\t\t\t-- manage counter\n";vhdl "\t\t\t\t\tif (controller_count < a + b - 1) then\n";vhdl "\t\t\t\t\t\tcontroller_count <= controller_count + 1;\n";vhdl "\t\t\t\t\telse\n";vhdl "\t\t\t\t\t\tcontroller_count <= 0;\n";vhdl "\t\t\t\t\tend if;\n";vhdl "\t\t\t\t\t-- decode counter\n";vhdl "\t\t\t\t\tif (controller_count < a) then\n";vhdl "\t\t\t\t\t\tmodulus_control <= '0';\n";vhdl "\t\t\t\t\telse\n";vhdl "\t\t\t\t\t\tmodulus_control <= '1';\n";vhdl "\t\t\t\t\tend if;\n";vhdl "\t\t\t\tend if;\n";vhdl "\t\t\tend if;\n";vhdl "\t\tend if;\n";vhdl "\tend process controller;\n";vhdl "end generate high_jitter_controller;\n";vhdl "\n";if ( $low_jitter_controller ) {    # low jitter controller    vhdl "low_jitter_controller : if minimum_jitter and not use_phase_accumulator and not use_recursive_controller generate\n";    vhdl "\tcontroller : process (async_reset, clock)\n";    vhdl "\tbegin\n";    vhdl "\t\tif (async_reset = '1') then\n";    my $odd_one_out = (($a < $b) or ($b == 0)) ? 1 : 0;    #$odd_one_out = 1;   # some chips might have problem with async sets    vhdl "\t\t\tmodulus_control <= " . ($odd_one_out ? "'0'" : "'1'") . ";\n";    vhdl "\t\t\tcontroller_count <= 0;\n";    vhdl "\t\telsif (rising_edge(clock)) then\n";    vhdl "\t\t\tif (clock_enable = '1') then\n";    vhdl "\t\t\t\tif (prescaler_out = '1') then\n";    vhdl "\t\t\t\t\t-- manage counter\n";    vhdl "\t\t\t\t\tif (controller_count < a + b - 1) then\n";    vhdl "\t\t\t\t\t\tcontroller_count <= controller_count + 1;\n";    vhdl "\t\t\t\t\telse\n";    vhdl "\t\t\t\t\t\tcontroller_count <= 0;\n";    vhdl "\t\t\t\t\tend if;\n";    vhdl "\t\t\t\t\t-- decode counter\n";    vhdl "\t\t\t\t\tif (controller_count <= a + b - 1) then\n";    vhdl "\t\t\t\t\t\tcase controller_count is\n";    if (($a + $b) > 1) {        vhdl "\t\t\t\t\t\t\twhen ";        my $num_printed = 0;        my $need_separator = 0;        for (my $index = 0; $index < $a + $b; $index++)        {            if ((substr $controller_table, $index, 1) == $odd_one_out) {                if ($num_printed > 7) {                    # wrap long lines                    vhdl " => modulus_control <= " . ($odd_one_out ? "'0'" : "'1'") . ";\n";                    vhdl "\t\t\t\t\t\t\twhen ";                    $num_printed = 0;                    $need_separator = 0;                }                vhdl (($need_separator ? "\|" : "") . $index);                $num_printed++;                $need_separator = 1;            }        }        vhdl " => modulus_control <= " . ($odd_one_out ? "'0'" : "'1'") . ";\n";    }    vhdl "\t\t\t\t\t\t\twhen others => modulus_control <= " . (($odd_one_out xor ($b == 0)) ? "'1'" : "'0'") . ";\n";    vhdl "\t\t\t\t\t\tend case;\n";    vhdl "\t\t\t\t\telse\n";    vhdl "\t\t\t\t\t\tmodulus_control <= '-';\t-- allow logic reductions (?)\n";    vhdl "\t\t\t\t\tend if;\n";    vhdl "\t\t\t\tend if;\n";    vhdl "\t\t\tend if;\n";    vhdl "\t\tend if;\n";    vhdl "\tend process controller;\n";    vhdl "end generate low_jitter_controller;\n";    vhdl "\n";}else {    vhdl "assert not minimum_jitter or use_recursive_controller or use_phase_accumulator\n";    vhdl "\treport \"Minimum jitter controller not available, as $0 was run with -g option\"\n";    vhdl "\tseverity failure;\n";    vhdl "\n";}verilog "/** this section not yet implemented in the Verilog version */\n\n";# recursive controllercomment_line;comment " recursive controller\n";comment " The modulus control signal for the prescaler can be generated by another\n";comment " fractional-N divider, which in turn can have its modulus control signal\n";comment " generated by yet another fractional-N divider, and so on.\n";comment " We stop when we don't need another fractional-N divider, and can just use\n";comment " a fixed divider.\n";comment " The p