--sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=4 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=10 denominator numerator quotient remainder
--VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_divide 2005:03:14:22:01:08:SJ cbx_mgl 2005:04:13:17:26:48:SJ cbx_stratix 2005:03:14:17:09:02:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END


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--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
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--  without limitation, that your use is for the sole purpose of 
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FUNCTION alt_u_div_3od (denominator[3..0], numerator[9..0])
RETURNS ( den_out[3..0], quotient[9..0], remainder[3..0]);
FUNCTION add_sub_ma8 (cin, dataa[3..0], datab[3..0])
RETURNS ( result[3..0]);

--synthesis_resources = lut 5 
SUBDESIGN sign_div_unsign_vig
( 
	denominator[3..0]	:	input;
	numerator[9..0]	:	input;
	quotient[9..0]	:	output;
	remainder[3..0]	:	output;
) 
VARIABLE 
	divider : alt_u_div_3od;
	adder : add_sub_ma8;
	adder_out[3..0]	: WIRE;
	gnd_wire	: WIRE;
	norm_num[9..0]	: WIRE;
	protect_quotient[9..0]	: WIRE;
	protect_remainder[3..0]	: WIRE;
	vcc_wire	: WIRE;

BEGIN 
	divider.denominator[] = denominator[];
	divider.numerator[] = norm_num[];
	adder.cin = gnd_wire;
	adder.dataa[] = denominator[];
	adder.datab[] = protect_remainder[];
	adder_out[] = adder.result[];
	gnd_wire = B"0";
	norm_num[] = numerator[];
	protect_quotient[] = divider.quotient[];
	protect_remainder[] = divider.remainder[];
	quotient[] = protect_quotient[];
	remainder[] = protect_remainder[];
	vcc_wire = B"1";
END;
--VALID FILE