-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--D1_flg1[2] is display:inst3|flg1[2]
--operation mode is normal

D1_flg1[2]_lut_out = D1_flg1[2] & (!D1_flg1[0]) # !D1_flg1[2] & D1_flg1[1] & D1_flg1[0];
D1_flg1[2] = DFFEAS(D1_flg1[2]_lut_out, F1_clk_out, VCC, , , , , , );


--D1_flg1[1] is display:inst3|flg1[1]
--operation mode is normal

D1_flg1[1]_lut_out = D1_flg1[1] & (!D1_flg1[0]) # !D1_flg1[1] & !D1_flg1[2] & D1_flg1[0];
D1_flg1[1] = DFFEAS(D1_flg1[1]_lut_out, F1_clk_out, VCC, , , , , , );


--D1L27 is display:inst3|led7s[6]~1740
--operation mode is normal

D1L27 = D1_flg1[2] & (!D1_flg1[1]);


--D1_flg1[0] is display:inst3|flg1[0]
--operation mode is normal

D1_flg1[0]_lut_out = !D1_flg1[0];
D1_flg1[0] = DFFEAS(D1_flg1[0]_lut_out, F1_clk_out, VCC, , , , , , );


--S6L1 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~44
--operation mode is normal

S6L1_carry_eqn = S6L3;
S6L1 = !S6L1_carry_eqn;


--S5L4 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~42
--operation mode is normal

S5L4_carry_eqn = S5L6;
S5L4 = !S5L4_carry_eqn;


--S91L4 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~41
--operation mode is normal

S91L4_carry_eqn = S91L01;
S91L4 = !S91L4_carry_eqn;


--S91_add_sub_cella[1] is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]
--operation mode is arithmetic

S91_add_sub_cella[1] = S5L4;

--S91L3 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUT
--operation mode is arithmetic

S91L3 = CARRY(S5L4);


--M3L91 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[46]~591
--operation mode is normal

M3L91 = S91L4 & (!S91_add_sub_cella[1]) # !S91L4 & S5L4;


--S91L5 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~46
--operation mode is arithmetic

S91L5_carry_eqn = S91L21;
S91L5 = S91L5_carry_eqn $ (!M3L31 & !M3L41);

--S91L6 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~48
--operation mode is arithmetic

S91L6 = CARRY(!M3L31 & !M3L41 & !S91L21);


--S81L4 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~41
--operation mode is normal

S81L4_carry_eqn = S81L8;
S81L4 = !S81L4_carry_eqn;


--S81_add_sub_cella[1] is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]
--operation mode is arithmetic

S81_add_sub_cella[1] = S4L4;

--S81L3 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]~COUT
--operation mode is arithmetic

S81L3 = CARRY(S4L4);


--M3L41 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[41]~18
--operation mode is normal

M3L41 = S81L4 & (!S81_add_sub_cella[1]);


--S4L4 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~42
--operation mode is normal

S4L4_carry_eqn = S4L6;
S4L4 = !S4L4_carry_eqn;


--M3L31 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[41]~13
--operation mode is normal

M3L31 = S4L4 & (!S81L4);


--M3L02 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[47]~592
--operation mode is normal

M3L02 = S91L4 & S91L5 # !S91L4 & (M3L41 # M3L31);


--S91L7 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~51
--operation mode is arithmetic

S91L7_carry_eqn = S91L6;
S91L7 = S91L7_carry_eqn $ (!M3L61 & !M3L51);

--S91L8 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~53
--operation mode is arithmetic

S91L8 = CARRY(!S91L6 & (M3L61 # M3L51));


--S3L4 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~42
--operation mode is normal

S3L4_carry_eqn = S3L6;
S3L4 = !S3L4_carry_eqn;


--S71L4 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~41
--operation mode is normal

S71L4_carry_eqn = S71L6;
S71L4 = !S71L4_carry_eqn;


--S71_add_sub_cella[1] is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]
--operation mode is arithmetic

S71_add_sub_cella[1] = S3L4;

--S71L3 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]~COUT
--operation mode is arithmetic

S71L3 = CARRY(S3L4);


--M3L61 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[42]~593
--operation mode is normal

M3L61 = !S81L4 & (S71L4 & (!S71_add_sub_cella[1]) # !S71L4 & S3L4);


--S81L5 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~46
--operation mode is arithmetic

S81L5_carry_eqn = S81L01;
S81L5 = S81L5_carry_eqn $ (!M3L7 & !M3L8);

--S81L6 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~48
--operation mode is arithmetic

S81L6 = CARRY(!M3L7 & !M3L8 & !S81L01);


--M3L51 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[42]~17
--operation mode is normal

M3L51 = S81L4 & S81L5;


--M3L12 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[48]~594
--operation mode is normal

M3L12 = S91L4 & S91L7 # !S91L4 & (M3L61 # M3L51);


--D1L73 is display:inst3|led7s5[6]~131
--operation mode is normal

D1L73 = M3L12 # M3L91 & (!M3L02 # !S6L1) # !M3L91 & (M3L02);


--Z3L1 is d_to_b:inst|lpm_divide:div_rtl_7|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~64
--operation mode is normal

Z3L1_carry_eqn = Z3L3;
Z3L1 = !Z3L1_carry_eqn;


--Z2L4 is d_to_b:inst|lpm_divide:div_rtl_7|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_8|add_sub_cella[3]~61
--operation mode is normal

Z2L4_carry_eqn = Z2L6;
Z2L4 = !Z2L4_carry_eqn;


--Z1L4 is d_to_b:inst|lpm_divide:div_rtl_7|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_7|add_sub_cella[3]~61
--operation mode is normal

Z1L4_carry_eqn = Z1L6;
Z1L4 = !Z1L4_carry_eqn;


--Y1L4 is d_to_b:inst|lpm_divide:div_rtl_7|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_qe8:add_sub_6|add_sub_cella[3]~52
--operation mode is normal

Y1L4_carry_eqn = Y1L6;
Y1L4 = Y1L4_carry_eqn;


--D1L14 is display:inst3|led7s6[6]~108
--operation mode is normal

D1L14 = Y1L4 # Z2L4 & (!Z1L4 # !Z3L1) # !Z2L4 & (Z1L4);


--D1L37 is display:inst3|led7s[6]~1741
--operation mode is normal

D1L37 = D1L27 & (D1_flg1[0] & (!D1L14) # !D1_flg1[0] & !D1L73);


--Z6L1 is d_to_b:inst1|lpm_divide:div_rtl_0|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~68
--operation mode is normal

Z6L1_carry_eqn = Z6L3;
Z6L1 = !Z6L1_carry_eqn;


--Z5L4 is d_to_b:inst1|lpm_divide:div_rtl_0|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_8|add_sub_cella[3]~61
--operation mode is normal

Z5L4_carry_eqn = Z5L6;
Z5L4 = !Z5L4_carry_eqn;


--Z4L4 is d_to_b:inst1|lpm_divide:div_rtl_0|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_7|add_sub_cella[3]~61
--operation mode is normal

Z4L4_carry_eqn = Z4L6;
Z4L4 = !Z4L4_carry_eqn;


--Y2L4 is d_to_b:inst1|lpm_divide:div_rtl_0|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_qe8:add_sub_6|add_sub_cella[3]~52
--operation mode is normal

Y2L4_carry_eqn = Y2L6;
Y2L4 = Y2L4_carry_eqn;


--D1L52 is display:inst3|led7s3[6]~133
--operation mode is normal

D1L52 = Y2L4 # Z5L4 & (!Z4L4 # !Z6L1) # !Z5L4 & (Z4L4);


--S62L1 is d_to_b:inst1|lpm_divide:div_rtl_1|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~48
--operation mode is normal

S62L1_carry_eqn = S62L3;
S62L1 = !S62L1_carry_eqn;


--S52L4 is d_to_b:inst1|lpm_divide:div_rtl_1|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~42
--operation mode is normal

S52L4_carry_eqn = S52L6;
S52L4 = !S52L4_carry_eqn;


--S23L4 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~41
--operation mode is normal

S23L4_carry_eqn = S23L01;
S23L4 = !S23L4_carry_eqn;


--S23_add_sub_cella[1] is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]
--operation mode is arithmetic

S23_add_sub_cella[1] = S52L4;

--S23L3 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUT
--operation mode is arithmetic

S23L3 = CARRY(S52L4);


--M5L91 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[46]~591
--operation mode is normal

M5L91 = S23L4 & (!S23_add_sub_cella[1]) # !S23L4 & S52L4;


--S23L5 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~46
--operation mode is arithmetic

S23L5_carry_eqn = S23L21;
S23L5 = S23L5_carry_eqn $ (!M5L31 & !M5L41);

--S23L6 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~48
--operation mode is arithmetic

S23L6 = CARRY(!M5L31 & !M5L41 & !S23L21);


--S13L4 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~41
--operation mode is normal

S13L4_carry_eqn = S13L8;
S13L4 = !S13L4_carry_eqn;


--S13_add_sub_cella[1] is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]
--operation mode is arithmetic

S13_add_sub_cella[1] = S42L4;

--S13L3 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]~COUT
--operation mode is arithmetic

S13L3 = CARRY(S42L4);


--M5L41 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[41]~18
--operation mode is normal

M5L41 = S13L4 & (!S13_add_sub_cella[1]);


--S42L4 is d_to_b:inst1|lpm_divide:div_rtl_1|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~42
--operation mode is normal

S42L4_carry_eqn = S42L6;
S42L4 = !S42L4_carry_eqn;


--M5L31 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[41]~13
--operation mode is normal

M5L31 = S42L4 & (!S13L4);


--M5L02 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[47]~592
--operation mode is normal

M5L02 = S23L4 & S23L5 # !S23L4 & (M5L41 # M5L31);


--S23L7 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~51
--operation mode is arithmetic

S23L7_carry_eqn = S23L6;
S23L7 = S23L7_carry_eqn $ (!M5L61 & !M5L51);

--S23L8 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~53
--operation mode is arithmetic

S23L8 = CARRY(!S23L6 & (M5L61 # M5L51));