--M3L7 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[36]~23
--operation mode is normal

M3L7 = S3L4 & (!S71L4);


--M3L8 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[36]~28
--operation mode is normal

M3L8 = S71L4 & (!S71_add_sub_cella[1]);


--S81L01 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~58
--operation mode is arithmetic

S81L01 = CARRY(S81L31);


--Z3L3 is d_to_b:inst|lpm_divide:div_rtl_7|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~71
--operation mode is arithmetic

Z3L3 = CARRY(!W1L23 & !W1L13 & !Z3L5);


--Z2L6 is d_to_b:inst|lpm_divide:div_rtl_7|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_8|add_sub_cella[3]~68
--operation mode is arithmetic

Z2L6 = CARRY(!W1L02 & !W1L91 & !Z2L8);


--Z1L6 is d_to_b:inst|lpm_divide:div_rtl_7|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_7|add_sub_cella[3]~68
--operation mode is arithmetic

Z1L6 = CARRY(!W1L9 & !W1L01 & !Z1L01);


--Y1L5 is d_to_b:inst|lpm_divide:div_rtl_7|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_qe8:add_sub_6|add_sub_cella[3]~57
--operation mode is arithmetic

Y1L5_carry_eqn = Y1L01;
Y1L5 = C1_stance[9] $ (!Y1L5_carry_eqn);

--Y1L6 is d_to_b:inst|lpm_divide:div_rtl_7|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_qe8:add_sub_6|add_sub_cella[3]~59
--operation mode is arithmetic

Y1L6 = CARRY(C1_stance[9] & (!Y1L01));


--Z6L3 is d_to_b:inst1|lpm_divide:div_rtl_0|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~75
--operation mode is arithmetic

Z6L3 = CARRY(!W2L23 & !W2L13 & !Z6L5);


--Z5L6 is d_to_b:inst1|lpm_divide:div_rtl_0|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_8|add_sub_cella[3]~68
--operation mode is arithmetic

Z5L6 = CARRY(!W2L02 & !W2L91 & !Z5L8);


--Z4L6 is d_to_b:inst1|lpm_divide:div_rtl_0|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_7|add_sub_cella[3]~68
--operation mode is arithmetic

Z4L6 = CARRY(!W2L9 & !W2L01 & !Z4L01);


--Y2L5 is d_to_b:inst1|lpm_divide:div_rtl_0|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_qe8:add_sub_6|add_sub_cella[3]~57
--operation mode is arithmetic

Y2L5_carry_eqn = Y2L01;
Y2L5 = C1_money[9] $ (!Y2L5_carry_eqn);

--Y2L6 is d_to_b:inst1|lpm_divide:div_rtl_0|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_qe8:add_sub_6|add_sub_cella[3]~59
--operation mode is arithmetic

Y2L6 = CARRY(C1_money[9] & (!Y2L01));


--S62L3 is d_to_b:inst1|lpm_divide:div_rtl_1|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~55
--operation mode is arithmetic

S62L3 = CARRY(!M4L83 & !M4L73 & !S62L5);


--S52L6 is d_to_b:inst1|lpm_divide:div_rtl_1|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~49
--operation mode is arithmetic

S52L6 = CARRY(!M4L03 & !M4L92 & !S52L8);


--S23L01 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~58
--operation mode is arithmetic

S23L01 = CARRY(!M5L81 & !M5L71 & !S23L8);


--S23L21 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~63
--operation mode is arithmetic

S23L21 = CARRY(S23L31);


--S13L8 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~53
--operation mode is arithmetic

S13L8 = CARRY(!M5L21 & !M5L11 & !S13L21);


--S42L6 is d_to_b:inst1|lpm_divide:div_rtl_1|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~49
--operation mode is arithmetic

S42L6 = CARRY(!M4L42 & !M4L32 & !S42L01);


--S32L6 is d_to_b:inst1|lpm_divide:div_rtl_1|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~49
--operation mode is arithmetic

S32L6 = CARRY(!M4L81 & !M4L71 & !S32L01);


--S03L6 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~48
--operation mode is arithmetic

S03L6 = CARRY(!M5L5 & !M5L6 & !S03L01);


--M5L7 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[36]~23
--operation mode is normal

M5L7 = S32L4 & (!S03L4);


--M5L8 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[36]~28
--operation mode is normal

M5L8 = S03L4 & (!S03_add_sub_cella[1]);


--S13L01 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~58
--operation mode is arithmetic

S13L01 = CARRY(S13L31);


--C1_time[0] is speed:inst2|time[0]
--operation mode is arithmetic

C1_time[0]_lut_out = !C1_time[0];
C1_time[0] = DFFEAS(C1_time[0]_lut_out, C1_mint, start, , , , , C1L601, );

--C1L602 is speed:inst2|time[0]~229
--operation mode is arithmetic

C1L602 = CARRY(C1_time[0]);


--C1_time[8] is speed:inst2|time[8]
--operation mode is arithmetic

C1_time[8]_carry_eqn = C1L022;
C1_time[8]_lut_out = C1_time[8] $ (!C1_time[8]_carry_eqn);
C1_time[8] = DFFEAS(C1_time[8]_lut_out, C1_mint, start, , , , , C1L601, );

--C1L222 is speed:inst2|time[8]~233
--operation mode is arithmetic

C1L222 = CARRY(C1_time[8] & (!C1L022));


--C1_time[2] is speed:inst2|time[2]
--operation mode is arithmetic

C1_time[2]_carry_eqn = C1L802;
C1_time[2]_lut_out = C1_time[2] $ (!C1_time[2]_carry_eqn);
C1_time[2] = DFFEAS(C1_time[2]_lut_out, C1_mint, start, , , , , C1L601, );

--C1L012 is speed:inst2|time[2]~237
--operation mode is arithmetic

C1L012 = CARRY(C1_time[2] & (!C1L802));


--C1_time[5] is speed:inst2|time[5]
--operation mode is arithmetic

C1_time[5]_carry_eqn = C1L412;
C1_time[5]_lut_out = C1_time[5] $ (C1_time[5]_carry_eqn);
C1_time[5] = DFFEAS(C1_time[5]_lut_out, C1_mint, start, , , , , C1L601, );

--C1L612 is speed:inst2|time[5]~241
--operation mode is arithmetic

C1L612 = CARRY(!C1L412 # !C1_time[5]);


--C1_time[6] is speed:inst2|time[6]
--operation mode is arithmetic

C1_time[6]_carry_eqn = C1L612;
C1_time[6]_lut_out = C1_time[6] $ (!C1_time[6]_carry_eqn);
C1_time[6] = DFFEAS(C1_time[6]_lut_out, C1_mint, start, , , , , C1L601, );

--C1L812 is speed:inst2|time[6]~245
--operation mode is arithmetic

C1L812 = CARRY(C1_time[6] & (!C1L612));


--C1_time[7] is speed:inst2|time[7]
--operation mode is arithmetic

C1_time[7]_carry_eqn = C1L812;
C1_time[7]_lut_out = C1_time[7] $ (C1_time[7]_carry_eqn);
C1_time[7] = DFFEAS(C1_time[7]_lut_out, C1_mint, start, , , , , C1L601, );

--C1L022 is speed:inst2|time[7]~249
--operation mode is arithmetic

C1L022 = CARRY(!C1L812 # !C1_time[7]);


--C1L741 is speed:inst2|process4~99
--operation mode is normal

C1L741 = C1_time[2] # C1_time[5] # C1_time[6] # C1_time[7];


--C1_time[3] is speed:inst2|time[3]
--operation mode is arithmetic

C1_time[3]_carry_eqn = C1L012;
C1_time[3]_lut_out = C1_time[3] $ (C1_time[3]_carry_eqn);
C1_time[3] = DFFEAS(C1_time[3]_lut_out, C1_mint, start, , , , , C1L601, );

--C1L212 is speed:inst2|time[3]~253
--operation mode is arithmetic

C1L212 = CARRY(!C1L012 # !C1_time[3]);


--C1_time[4] is speed:inst2|time[4]
--operation mode is arithmetic

C1_time[4]_carry_eqn = C1L212;
C1_time[4]_lut_out = C1_time[4] $ (!C1_time[4]_carry_eqn);
C1_time[4] = DFFEAS(C1_time[4]_lut_out, C1_mint, start, , , , , C1L601, );

--C1L412 is speed:inst2|time[4]~257
--operation mode is arithmetic

C1L412 = CARRY(C1_time[4] & (!C1L212));


--C1L301 is speed:inst2|LessThan~719
--operation mode is normal

C1L301 = !C1_time[3] & !C1_time[4];


--C1_time[1] is speed:inst2|time[1]
--operation mode is arithmetic

C1_time[1]_carry_eqn = C1L602;
C1_time[1]_lut_out = C1_time[1] $ (C1_time[1]_carry_eqn);
C1_time[1] = DFFEAS(C1_time[1]_lut_out, C1_mint, start, , , , , C1L601, );

--C1L802 is speed:inst2|time[1]~261
--operation mode is arithmetic

C1L802 = CARRY(!C1L602 # !C1_time[1]);


--C1_time[9] is speed:inst2|time[9]
--operation mode is normal

C1_time[9]_carry_eqn = C1L222;
C1_time[9]_lut_out = C1_time[9] $ (C1_time[9]_carry_eqn);
C1_time[9] = DFFEAS(C1_time[9]_lut_out, C1_mint, start, , , , , C1L601, );


--C1L841 is speed:inst2|process4~100
--operation mode is normal

C1L841 = C1_time[0] # C1_time[1] # C1_time[9] # push;


--C1L941 is speed:inst2|process4~101
--operation mode is normal

C1L941 = C1_time[8] # C1L741 # C1L841 # !C1L301;


--E1_clk_out is frq:inst4|clk_out
--operation mode is normal

E1_clk_out_lut_out = !E1_clk_out;
E1_clk_out = DFFEAS(E1_clk_out_lut_out, E1_clk2, VCC, , , , , , );


--S83L01 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~58
--operation mode is arithmetic

S83L01 = CARRY(!M6L63 & !M6L53 & !S83L8);


--C1_money[1] is speed:inst2|money[1]
--operation mode is normal

C1_money[1]_lut_out = C1L331 # C1L431;
C1_money[1] = DFFEAS(C1_money[1]_lut_out, E1_clk_out, VCC, , , , , , );


--M6L13 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[41]~13
--operation mode is normal

M6L13 = S73_add_sub_cella[1] & (!S73L4);


--M6L23 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[41]~18
--operation mode is normal

M6L23 = S73L4 & (!S73_add_sub_cella[1]);


--S83L21 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~63
--operation mode is arithmetic

S83L21 = CARRY(S83L31);


--S73L8 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~53
--operation mode is arithmetic

S73L8 = CARRY(!M6L03 & !M6L92 & !S73L21);


--C1_money[2] is speed:inst2|money[2]
--operation mode is normal

C1_money[2]_lut_out = C1L531 # C1L631;
C1_money[2] = DFFEAS(C1_money[2]_lut_out, E1_clk_out, VCC, , , , , , );


--S63L6 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~48
--operation mode is arithmetic

S63L6 = CARRY(!M6L42 & !M6L32 & !S63L01);


--C1_money[3] is speed:inst2|money[3]
--operation mode is normal

C1_money[3]_lut_out = C1L731 # C1L831;
C1_money[3] = DFFEAS(C1_money[3]_lut_out, E1_clk_out, VCC, , , , , , );


--M6L52 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[36]~23
--operation mode is normal

M6L52 = S63_add_sub_cella[1] & (!S63L4);


--M6L62 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[36]~28
--operation mode is normal

M6L62 = S63L4 & (!S63_add_sub_cella[1]);


--S73L01 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~58
--operation mode is arithmetic

S73L01 = CARRY(S73L31);


--C1L1 is speed:inst2|add~1610
--operation mode is arithmetic

C1L1 = !C1_q3[0];

--C1L2 is speed:inst2|add~1612
--operation mode is arithmetic