?? shuma.tan.rpt
字號(hào):
Timing Analyzer report for shuma
Sat May 16 15:19:33 2009
Version 4.1 Build 181 06/29/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Settings
3. Timing Analyzer Summary
4. Clock Settings Summary
5. Clock Setup: 'CLK'
6. tco
7. Minimum tco
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+
; Option ; Setting ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name ; EPM7128SLC84-15 ; ; ;
; Timing Models ; Production ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ;
; Number of destination nodes to report ; 10 ; ; ;
; Number of paths to report ; 200 ; ; ;
; Run Minimum Analysis ; On ; ; ;
; Use Minimum Timing Models ; Off ; ; ;
; Report IO Paths Separately ; Off ; ; ;
; Clock Analysis Only ; Off ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ;
; Cut off read during write signal paths ; On ; ; ;
; Cut off clear and preset signal paths ; On ; ; ;
; Cut off feedback from I/O pins ; On ; ; ;
; Ignore Clock Settings ; Off ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ;
+-------------------------------------------------------+--------------------+------+----+
+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+--------+---------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+--------+---------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 17.000 ns ; o[6] ; yout[3] ; CLK ; ; 0 ;
; Worst-case Minimum tco ; N/A ; None ; 8.000 ns ; con[4] ; cat[4] ; CLK ; ; 0 ;
; Clock Setup: 'CLK' ; N/A ; None ; 66.67 MHz ( period = 15.000 ns ) ; o[0] ; o[7] ; CLK ; CLK ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+--------+---------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK' ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 66.67 MHz ( period = 15.000 ns ) ; o[8] ; o[2] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 66.67 MHz ( period = 15.000 ns ) ; o[9] ; o[2] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 66.67 MHz ( period = 15.000 ns ) ; o[4] ; o[2] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 66.67 MHz ( period = 15.000 ns ) ; o[1] ; o[2] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 66.67 MHz ( period = 15.000 ns ) ; o[6] ; o[2] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 66.67 MHz ( period = 15.000 ns ) ; o[5] ; o[2] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 66.67 MHz ( period = 15.000 ns ) ; o[2] ; o[2] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 66.67 MHz ( period = 15.000 ns ) ; o[0] ; o[2] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 66.67 MHz ( period = 15.000 ns ) ; o[7] ; o[7] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 66.67 MHz ( period = 15.000 ns ) ; o[8] ; o[7] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 66.67 MHz ( period = 15.000 ns ) ; o[9] ; o[7] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 66.67 MHz ( period = 15.000 ns ) ; o[4] ; o[7] ; CLK ; CLK ; None ; None ; None ;
; N/A ; 66.67 MHz ( period = 15.000 ns ) ; o[1] ; o[7] ; CLK ; CLK ; None ; None ; None ;
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