+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+--------+---------+------------+
; Slack ; Required tco ; Actual tco ; From   ; To      ; From Clock ;
+-------+--------------+------------+--------+---------+------------+
; N/A   ; None         ; 17.000 ns  ; o[6]   ; yout[3] ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; o[9]   ; yout[9] ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; o[8]   ; yout[8] ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; o[2]   ; yout[2] ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; o[4]   ; yout[4] ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; o[6]   ; yout[6] ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; o[0]   ; yout[0] ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; con[5] ; cat[5]  ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; o[5]   ; yout[5] ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; con[1] ; cat[1]  ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; con[0] ; cat[0]  ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; o[1]   ; yout[1] ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; con[3] ; cat[3]  ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; con[2] ; cat[2]  ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; o[7]   ; yout[7] ; CLK        ;
; N/A   ; None         ; 8.000 ns   ; con[4] ; cat[4]  ; CLK        ;
+-------+--------------+------------+--------+---------+------------+


+-----------------------------------------------------------------------------------+
; Minimum tco                                                                       ;
+---------------+------------------+----------------+--------+---------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From   ; To      ; From Clock ;
+---------------+------------------+----------------+--------+---------+------------+
; N/A           ; None             ; 8.000 ns       ; con[4] ; cat[4]  ; CLK        ;
; N/A           ; None             ; 8.000 ns       ; o[7]   ; yout[7] ; CLK        ;
; N/A           ; None             ; 8.000 ns       ; con[2] ; cat[2]  ; CLK        ;
; N/A           ; None             ; 8.000 ns       ; con[3] ; cat[3]  ; CLK        ;
; N/A           ; None             ; 8.000 ns       ; o[1]   ; yout[1] ; CLK        ;
; N/A           ; None             ; 8.000 ns       ; con[0] ; cat[0]  ; CLK        ;
; N/A           ; None             ; 8.000 ns       ; con[1] ; cat[1]  ; CLK        ;
; N/A           ; None             ; 8.000 ns       ; o[5]   ; yout[5] ; CLK        ;
; N/A           ; None             ; 8.000 ns       ; con[5] ; cat[5]  ; CLK        ;
; N/A           ; None             ; 8.000 ns       ; o[0]   ; yout[0] ; CLK        ;
; N/A           ; None             ; 8.000 ns       ; o[6]   ; yout[6] ; CLK        ;
; N/A           ; None             ; 8.000 ns       ; o[4]   ; yout[4] ; CLK        ;
; N/A           ; None             ; 8.000 ns       ; o[2]   ; yout[2] ; CLK        ;
; N/A           ; None             ; 8.000 ns       ; o[8]   ; yout[8] ; CLK        ;
; N/A           ; None             ; 8.000 ns       ; o[9]   ; yout[9] ; CLK        ;
; N/A           ; None             ; 17.000 ns      ; o[6]   ; yout[3] ; CLK        ;
+---------------+------------------+----------------+--------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sat May 16 15:19:33 2009
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off shuma -c shuma
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node CLK is an undefined clock
Info: Clock CLK has Internal fmax of 66.67 MHz between source register o[8] and destination register o[2] (period= 15.0 ns)
    Info: + Longest register to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 49; REG Node = 'o[8]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC9; Fanout = 1; COMB Node = 'reduce_or~5503'
        Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC10; Fanout = 1; COMB Node = 'reduce_or~5505'
        Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 10.000 ns; Loc. = LC11; Fanout = 66; REG Node = 'o[2]'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock CLK to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 15; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC11; Fanout = 66; REG Node = 'o[2]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock CLK to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 15; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC5; Fanout = 49; REG Node = 'o[8]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tco from clock CLK to destination pin yout[3] through register o[6] is 17.000 ns
    Info: + Longest clock path from clock CLK to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 15; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 67; REG Node = 'o[6]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 13.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 67; REG Node = 'o[6]'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC37; Fanout = 1; COMB Node = 'o[6]~183'
        Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'yout[3]'
        Info: Total cell delay = 11.000 ns ( 84.62 % )
        Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: Minimum tco from clock CLK to destination pin cat[4] through register con[4] is 8.000 ns
    Info: + Shortest clock path from clock CLK to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 15; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC17; Fanout = 11; REG Node = 'con[4]'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Shortest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 11; REG Node = 'con[4]'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_22; Fanout = 0; PIN Node = 'cat[4]'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat May 16 15:19:33 2009
    Info: Elapsed time: 00:00:00