{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register o\[8\] register o\[2\] 66.67 MHz 15.0 ns Internal " "Info: Clock CLK has Internal fmax of 66.67 MHz between source register o\[8\] and destination register o\[2\] (period= 15.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest register register " "Info: + Longest register to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns o\[8\] 1 REG LC5 49 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 49; REG Node = 'o\[8\]'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "" { o[8] } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns reduce_or~5503 2 COMB LC9 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC9; Fanout = 1; COMB Node = 'reduce_or~5503'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "8.000 ns" { o[8] reduce_or~5503 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns reduce_or~5505 3 COMB LC10 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC10; Fanout = 1; COMB Node = 'reduce_or~5505'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "1.000 ns" { reduce_or~5503 reduce_or~5505 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 10.000 ns o\[2\] 4 REG LC11 66 " "Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 10.000 ns; Loc. = LC11; Fanout = 66; REG Node = 'o\[2\]'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "1.000 ns" { reduce_or~5505 o[2] } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "10.000 ns" { o[8] reduce_or~5503 reduce_or~5505 o[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock CLK to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 15 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 15; CLK Node = 'CLK'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns o\[2\] 2 REG LC11 66 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC11; Fanout = 66; REG Node = 'o\[2\]'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "0.000 ns" { CLK o[2] } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "3.000 ns" { CLK o[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.000 ns - Longest register " "Info: - Longest clock path from clock CLK to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 15 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 15; CLK Node = 'CLK'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns o\[8\] 2 REG LC5 49 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC5; Fanout = 49; REG Node = 'o\[8\]'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "0.000 ns" { CLK o[8] } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "3.000 ns" { CLK o[8] } "NODE_NAME" } } }  } 0}  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "3.000 ns" { CLK o[2] } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "3.000 ns" { CLK o[8] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 28 -1 0 } }  } 0}  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "10.000 ns" { o[8] reduce_or~5503 reduce_or~5505 o[2] } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "3.000 ns" { CLK o[2] } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "3.000 ns" { CLK o[8] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK yout\[3\] o\[6\] 17.000 ns register " "Info: tco from clock CLK to destination pin yout\[3\] through register o\[6\] is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.000 ns + Longest register " "Info: + Longest clock path from clock CLK to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 15 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 15; CLK Node = 'CLK'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns o\[6\] 2 REG LC8 67 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 67; REG Node = 'o\[6\]'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "0.000 ns" { CLK o[6] } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "3.000 ns" { CLK o[6] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns o\[6\] 1 REG LC8 67 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 67; REG Node = 'o\[6\]'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "" { o[6] } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns o\[6\]~183 2 COMB LC37 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC37; Fanout = 1; COMB Node = 'o\[6\]~183'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "9.000 ns" { o[6] o[6]~183 } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns yout\[3\] 3 PIN PIN_30 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'yout\[3\]'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "4.000 ns" { o[6]~183 yout[3] } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.000 ns 84.62 % " "Info: Total cell delay = 11.000 ns ( 84.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.38 % " "Info: Total interconnect delay = 2.000 ns ( 15.38 % )" {  } {  } 0}  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "13.000 ns" { o[6] o[6]~183 yout[3] } "NODE_NAME" } } }  } 0}  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "3.000 ns" { CLK o[6] } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "13.000 ns" { o[6] o[6]~183 yout[3] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CLK cat\[4\] con\[4\] 8.000 ns register " "Info: Minimum tco from clock CLK to destination pin cat\[4\] through register con\[4\] is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.000 ns + Shortest register " "Info: + Shortest clock path from clock CLK to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 15 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 15; CLK Node = 'CLK'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns con\[4\] 2 REG LC17 11 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC17; Fanout = 11; REG Node = 'con\[4\]'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "0.000 ns" { CLK con[4] } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "3.000 ns" { CLK con[4] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns con\[4\] 1 REG LC17 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 11; REG Node = 'con\[4\]'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "" { con[4] } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns cat\[4\] 2 PIN PIN_22 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_22; Fanout = 0; PIN Node = 'cat\[4\]'" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "4.000 ns" { con[4] cat[4] } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "4.000 ns" { con[4] cat[4] } "NODE_NAME" } } }  } 0}  } { { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "3.000 ns" { CLK con[4] } "NODE_NAME" } } } { "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" "" "" { Report "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma_cmp.qrpt" Compiler "shuma" "UNKNOWN" "V1" "g:/program files/quartus/altera/work/實驗四/shuma/db/shuma.quartus_db" { Floorplan "" "" "4.000 ns" { con[4] cat[4] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 16 15:19:33 2009 " "Info: Processing ended: Sat May 16 15:19:33 2009" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}