{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 16 15:19:26 2009 " "Info: Processing started: Sat May 16 15:19:26 2009" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off shuma -c shuma " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off shuma -c shuma" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shuma.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file shuma.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shuma-code " "Info: Found design unit 1: shuma-code" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "shuma-code" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 shuma " "Info: Found entity 1: shuma" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "shuma" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "o\[3\] o\[6\] " "Info: Duplicate register o\[3\] merged to single register o\[6\]" {  } { { "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" "" "" { Text "g:/program files/quartus/altera/work/實驗四/shuma/shuma.vhd" 28 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "CLK " "Info: Promoted clock signal driven by pin CLK to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "42 " "Info: Implemented 42 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "25 " "Info: Implemented 25 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 16 15:19:28 2009 " "Info: Processing ended: Sat May 16 15:19:28 2009" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}