// Copyright (C) 1991-2008 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 8.1 Build 163 10/28/2008 SJ Full Version"

// DATE "03/23/2009 21:19:46"

// 
// Device: Altera EPM240T100C5 Package TQFP100
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module sram_test (
	clk,
	rst_n,
	led,
	sram_addr,
	sram_wr_n,
	sram_data);
input 	clk;
input 	rst_n;
output 	led;
output 	[14:0] sram_addr;
output 	sram_wr_n;
inout 	[7:0] sram_data;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("sram_test_v.sdo");
// synopsys translate_on

wire \addr_r[8]~146_cout ;
wire \addr_r[8]~149_cout ;
wire \addr_r[8]~152_cout ;
wire \addr_r[8]~155_cout ;
wire \addr_r[8]~161_cout ;
wire \sram_data[0]~15 ;
wire \sram_data[1]~14 ;
wire \sram_data[2]~13 ;
wire \sram_data[3]~12 ;
wire \sram_data[4]~11 ;
wire \sram_data[5]~10 ;
wire \sram_data[6]~9 ;
wire \sram_data[7]~8 ;
wire \clk~combout ;
wire \rst_n~combout ;
wire \delay[1]~128 ;
wire \delay[1]~128COUT1_199 ;
wire \delay[2]~172 ;
wire \delay[3]~174 ;
wire \delay[3]~174COUT1_201 ;
wire \delay[4]~176 ;
wire \delay[4]~176COUT1_203 ;
wire \delay[5]~158 ;
wire \delay[5]~158COUT1_205 ;
wire \delay[6]~132 ;
wire \delay[6]~132COUT1_207 ;
wire \delay[7]~170 ;
wire \delay[8]~168 ;
wire \delay[8]~168COUT1_209 ;
wire \delay[9]~156 ;
wire \delay[9]~156COUT1_211 ;
wire \delay[10]~130 ;
wire \delay[10]~130COUT1_213 ;
wire \delay[11]~162 ;
wire \delay[11]~162COUT1_215 ;
wire \delay[12]~160 ;
wire \delay[13]~166 ;
wire \delay[13]~166COUT1_217 ;
wire \Equal2~79_combout ;
wire \Equal1~117_combout ;
wire \delay[14]~164 ;
wire \delay[14]~164COUT1_219 ;
wire \delay[15]~134 ;
wire \delay[15]~134COUT1_221 ;
wire \delay[16]~136 ;
wire \delay[16]~136COUT1_223 ;
wire \delay[17]~138 ;
wire \delay[18]~140 ;
wire \delay[18]~140COUT1_225 ;
wire \delay[19]~142 ;
wire \delay[19]~142COUT1_227 ;
wire \delay[20]~144 ;
wire \delay[20]~144COUT1_229 ;
wire \delay[21]~146 ;
wire \delay[21]~146COUT1_231 ;
wire \Equal0~218_combout ;
wire \Equal0~216_combout ;
wire \Equal0~217_combout ;
wire \delay[22]~148 ;
wire \delay[23]~150 ;
wire \delay[23]~150COUT1_233 ;
wire \delay[24]~152 ;
wire \delay[24]~152COUT1_235 ;
wire \Equal0~219_combout ;
wire \Equal0~220_combout ;
wire \Equal0~222_combout ;
wire \Equal0~223_combout ;
wire \Equal2~80_combout ;
wire \wr_data[1]~86 ;
wire \wr_data[1]~86COUT1_107 ;
wire \wr_data[2]~88 ;
wire \wr_data[2]~88COUT1_109 ;
wire \wr_data[3]~90 ;
wire \wr_data[3]~90COUT1_111 ;
wire \wr_data[4]~92 ;
wire \Equal5~15_combout ;
wire \Equal0~221_combout ;
wire \Equal0~224_combout ;
wire \cstate.WRT0~regout ;
wire \cstate.WRT1~regout ;
wire \Selector0~47_combout ;
wire \Equal1~115_combout ;
wire \Equal1~116_combout ;
wire \Equal1~118_combout ;
wire \cstate.IDLE~regout ;
wire \cstate.REA0~regout ;
wire \cstate.REA1~regout ;
wire \led_r~48 ;
wire \wr_data[5]~94 ;
wire \wr_data[5]~94COUT1_113 ;
wire \wr_data[6]~96 ;
wire \wr_data[6]~96COUT1_115 ;
wire \led_r~46 ;
wire \led_r~47 ;
wire \led_r~45 ;
wire \led_r~49_combout ;
wire \Equal3~80_combout ;
wire \led_r~regout ;
wire \addr_r[8]~161COUT0_184 ;
wire \addr_r[8]~161COUT1_185 ;
wire \addr_r[8]~158_cout ;
wire \addr_r[8]~155COUT0_187 ;
wire \addr_r[8]~155COUT1_188 ;
wire \addr_r[8]~152COUT0_190 ;
wire \addr_r[8]~152COUT1_191 ;
wire \addr_r[8]~149COUT0_193 ;
wire \addr_r[8]~149COUT1_194 ;
wire \addr_r[8]~146COUT0_196 ;
wire \addr_r[8]~146COUT1_197 ;
wire \addr_r[8]~143_cout ;
wire \addr_r[8]~128 ;
wire \addr_r[8]~128COUT1_199 ;
wire \addr_r[9]~130 ;
wire \addr_r[9]~130COUT1_201 ;
wire \addr_r[10]~132 ;
wire \addr_r[10]~132COUT1_203 ;
wire \addr_r[11]~134 ;
wire \addr_r[11]~134COUT1_205 ;
wire \addr_r[12]~136 ;
wire \addr_r[13]~138 ;
wire \addr_r[13]~138COUT1_207 ;
wire \sdlink~regout ;
wire [14:0] addr_r;
wire [2:0] cnt;
wire [25:0] delay;
wire [7:0] rd_data;
wire [7:0] wr_data;


// atom is at PIN_54
maxii_io \sram_data[0]~I (
	.datain(wr_data[0]),
	.oe(\sdlink~regout ),
	.combout(\sram_data[0]~15 ),
	.padio(sram_data[0]));
// synopsys translate_off
defparam \sram_data[0]~I .operation_mode = "bidir";
// synopsys translate_on

// atom is at PIN_53
maxii_io \sram_data[1]~I (
	.datain(wr_data[1]),
	.oe(\sdlink~regout ),
	.combout(\sram_data[1]~14 ),
	.padio(sram_data[1]));
// synopsys translate_off
defparam \sram_data[1]~I .operation_mode = "bidir";
// synopsys translate_on

// atom is at PIN_52
maxii_io \sram_data[2]~I (
	.datain(wr_data[2]),
	.oe(\sdlink~regout ),
	.combout(\sram_data[2]~13 ),
	.padio(sram_data[2]));
// synopsys translate_off
defparam \sram_data[2]~I .operation_mode = "bidir";
// synopsys translate_on

// atom is at PIN_47
maxii_io \sram_data[3]~I (
	.datain(wr_data[3]),
	.oe(\sdlink~regout ),
	.combout(\sram_data[3]~12 ),
	.padio(sram_data[3]));
// synopsys translate_off
defparam \sram_data[3]~I .operation_mode = "bidir";
// synopsys translate_on

// atom is at PIN_48
maxii_io \sram_data[4]~I (
	.datain(wr_data[4]),
	.oe(\sdlink~regout ),
	.combout(\sram_data[4]~11 ),
	.padio(sram_data[4]));
// synopsys translate_off
defparam \sram_data[4]~I .operation_mode = "bidir";
// synopsys translate_on

// atom is at PIN_49
maxii_io \sram_data[5]~I (
	.datain(wr_data[5]),
	.oe(\sdlink~regout ),
	.combout(\sram_data[5]~10 ),
	.padio(sram_data[5]));
// synopsys translate_off
defparam \sram_data[5]~I .operation_mode = "bidir";
// synopsys translate_on

// atom is at PIN_50
maxii_io \sram_data[6]~I (
	.datain(wr_data[6]),
	.oe(\sdlink~regout ),
	.combout(\sram_data[6]~9 ),
	.padio(sram_data[6]));
// synopsys translate_off
defparam \sram_data[6]~I .operation_mode = "bidir";
// synopsys translate_on

// atom is at PIN_51
maxii_io \sram_data[7]~I (
	.datain(wr_data[7]),
	.oe(\sdlink~regout ),
	.combout(\sram_data[7]~8 ),
	.padio(sram_data[7]));
// synopsys translate_off
defparam \sram_data[7]~I .operation_mode = "bidir";
// synopsys translate_on

// atom is at PIN_12
maxii_io \clk~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\clk~combout ),
	.padio(clk));
// synopsys translate_off
defparam \clk~I .operation_mode = "input";
// synopsys translate_on

// atom is at PIN_44
maxii_io \rst_n~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\rst_n~combout ),
	.padio(rst_n));
// synopsys translate_off
defparam \rst_n~I .operation_mode = "input";
// synopsys translate_on

// atom is at LC_X5_Y3_N2
maxii_lcell \delay[0] (
// Equation(s):
// delay[0] = DFFEAS(!delay[0], GLOBAL(\clk~combout ), GLOBAL(\rst_n~combout ), , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(delay[0]),
	.aclr(!\rst_n~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(delay[0]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \delay[0] .lut_mask = "00ff";
defparam \delay[0] .operation_mode = "normal";
defparam \delay[0] .output_mode = "reg_only";
defparam \delay[0] .register_cascade_mode = "off";
defparam \delay[0] .sum_lutc_input = "datac";
defparam \delay[0] .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X5_Y3_N3
maxii_lcell \delay[1] (
// Equation(s):
// delay[1] = DFFEAS(delay[1] $ delay[0], GLOBAL(\clk~combout ), GLOBAL(\rst_n~combout ), , , , , , )
// \delay[1]~128  = CARRY(delay[1] & delay[0])
// \delay[1]~128COUT1_199  = CARRY(delay[1] & delay[0])

	.clk(\clk~combout ),
	.dataa(delay[1]),
	.datab(delay[0]),
	.datac(vcc),
	.datad(vcc),
	.aclr(!\rst_n~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(delay[1]),
	.cout(),
	.cout0(\delay[1]~128 ),
	.cout1(\delay[1]~128COUT1_199 ));
// synopsys translate_off
defparam \delay[1] .lut_mask = "6688";
defparam \delay[1] .operation_mode = "arithmetic";
defparam \delay[1] .output_mode = "reg_only";
defparam \delay[1] .register_cascade_mode = "off";
defparam \delay[1] .sum_lutc_input = "datac";
defparam \delay[1] .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X5_Y3_N4
maxii_lcell \delay[2] (
// Equation(s):
// delay[2] = DFFEAS(delay[2] $ (\delay[1]~128 ), GLOBAL(\clk~combout ), GLOBAL(\rst_n~combout ), , , , , , )
// \delay[2]~172  = CARRY(!\delay[1]~128COUT1_199  # !delay[2])

	.clk(\clk~combout ),
	.dataa(delay[2]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(!\rst_n~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\delay[1]~128 ),
	.cin1(\delay[1]~128COUT1_199 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(delay[2]),
	.cout(\delay[2]~172 ),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \delay[2] .cin0_used = "true";
defparam \delay[2] .cin1_used = "true";
defparam \delay[2] .lut_mask = "5a5f";
defparam \delay[2] .operation_mode = "arithmetic";
defparam \delay[2] .output_mode = "reg_only";
defparam \delay[2] .register_cascade_mode = "off";
defparam \delay[2] .sum_lutc_input = "cin";
defparam \delay[2] .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X5_Y3_N5
maxii_lcell \delay[3] (
// Equation(s):
// delay[3] = DFFEAS(delay[3] $ (!\delay[2]~172 ), GLOBAL(\clk~combout ), GLOBAL(\rst_n~combout ), , , , , , )
// \delay[3]~174  = CARRY(delay[3] & (!\delay[2]~172 ))
// \delay[3]~174COUT1_201  = CARRY(delay[3] & (!\delay[2]~172 ))

	.clk(\clk~combout ),
	.dataa(delay[3]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(!\rst_n~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(\delay[2]~172 ),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(delay[3]),
	.cout(),
	.cout0(\delay[3]~174 ),
	.cout1(\delay[3]~174COUT1_201 ));
// synopsys translate_off
defparam \delay[3] .cin_used = "true";
defparam \delay[3] .lut_mask = "a50a";
defparam \delay[3] .operation_mode = "arithmetic";
defparam \delay[3] .output_mode = "reg_only";
defparam \delay[3] .register_cascade_mode = "off";
defparam \delay[3] .sum_lutc_input = "cin";
defparam \delay[3] .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X5_Y3_N6
maxii_lcell \delay[4] (
// Equation(s):
// delay[4] = DFFEAS(delay[4] $ ((!\delay[2]~172  & \delay[3]~174 ) # (\delay[2]~172  & \delay[3]~174COUT1_201 )), GLOBAL(\clk~combout ), GLOBAL(\rst_n~combout ), , , , , , )
// \delay[4]~176  = CARRY(!\delay[3]~174  # !delay[4])
// \delay[4]~176COUT1_203  = CARRY(!\delay[3]~174COUT1_201  # !delay[4])

	.clk(\clk~combout ),
	.dataa(delay[4]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(!\rst_n~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(\delay[2]~172 ),
	.cin0(\delay[3]~174 ),
	.cin1(\delay[3]~174COUT1_201 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(delay[4]),
	.cout(),
	.cout0(\delay[4]~176 ),
	.cout1(\delay[4]~176COUT1_203 ));
// synopsys translate_off
defparam \delay[4] .cin0_used = "true";
defparam \delay[4] .cin1_used = "true";
defparam \delay[4] .cin_used = "true";
defparam \delay[4] .lut_mask = "5a5f";
defparam \delay[4] .operation_mode = "arithmetic";
defparam \delay[4] .output_mode = "reg_only";
defparam \delay[4] .register_cascade_mode = "off";
defparam \delay[4] .sum_lutc_input = "cin";
defparam \delay[4] .synch_mode = "off";
// synopsys translate_on