vendor_name = ModelSim
source_file = 1, C:/franchiese/FPGA文檔資料/altera設計實例/MAX II和MAX設計實例/an496_design_example/myosctest/myosctest.v
source_file = 1, C:/franchiese/FPGA文檔資料/altera設計實例/MAX II和MAX設計實例/an496_design_example/myosctest/internal_osc.qip
source_file = 1, C:/franchiese/FPGA文檔資料/altera設計實例/MAX II和MAX設計實例/an496_design_example/myosctest/internal_osc.v
source_file = 1, C:/franchiese/FPGA文檔資料/altera設計實例/MAX II和MAX設計實例/an496_design_example/myosctest/vwf_myosctest.vwf
source_file = 1, C:/franchiese/FPGA文檔資料/altera設計實例/MAX II和MAX設計實例/an496_design_example/myosctest/db/myosctest.cbx.xml
source_file = 1, none
design_name = myosctest
instance = comp, \~GND , ~GND, myosctest, 1
instance = comp, \internal_osc|internal_osc_altufm_osc_rv5_component|maxii_ufm_block1 , internal_osc|internal_osc_altufm_osc_rv5_component|maxii_ufm_block1, myosctest, 1
instance = comp, \rst_n~I , rst_n, myosctest, 1
instance = comp, \cnt[0] , cnt[0], myosctest, 1
instance = comp, \cnt[1] , cnt[1], myosctest, 1
instance = comp, \cnt[2] , cnt[2], myosctest, 1
instance = comp, \clkdiv~I , clkdiv, myosctest, 1