?? maxii_atoms.v
字號:
buf (isload, sload);
buf (iena, ena);
buf (idatac, datac);
buf (iregcascin, regcascin);
buf (idatain, datain);
assign reset = devpor && devclrn && (!iaclr) && (iena);
assign nosload = reset && (!isload);
specify
$setuphold (posedge clk &&& reset, regcascin, 0, 0, regcascin_viol) ;
$setuphold (posedge clk &&& nosload, datain, 0, 0, datain_viol) ;
$setuphold (posedge clk &&& reset, datac, 0, 0, datac_viol) ;
$setuphold (posedge clk &&& reset, sclr, 0, 0, sclr_viol) ;
$setuphold (posedge clk &&& reset, sload, 0, 0, sload_viol) ;
$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;
(posedge clk => (regout +: iregout)) = 0 ;
(posedge aclr => (regout +: 1'b0)) = (0, 0) ;
(posedge aload => (regout +: iregout)) = (0, 0) ;
(datac => regout) = (0, 0) ;
(posedge clk => (qfbkout +: iregout)) = 0 ;
(posedge aclr => (qfbkout +: 1'b0)) = (0, 0) ;
(posedge aload => (qfbkout +: iregout)) = (0, 0) ;
(datac => qfbkout) = (0, 0) ;
endspecify
initial
begin
violation = 0;
clk_last_value = 'b0;
if (power_up == "low")
begin
iregout <= 'b0;
ipower_up = 0;
end
else if (power_up == "high")
begin
iregout <= 'b1;
ipower_up = 1;
end
if (register_cascade_mode == "on")
icascade_mode = 1;
else
icascade_mode = 0;
if (synch_mode == "on" )
isynch_mode = 1;
else
isynch_mode = 0;
if (x_on_violation == "on")
ix_on_violation = 1;
else
ix_on_violation = 0;
end
always @ (regcascin_viol or datain_viol or datac_viol or sclr_viol
or sload_viol or ena_viol or clk_per_viol)
begin
if (ix_on_violation == 1)
violation = 1;
end
always @ (clk_in or idatac or iaclr or posedge iaload
or devclrn or devpor or posedge violation)
begin
if (violation == 1'b1)
begin
violation = 0;
iregout <= 'bx;
end
else
begin
if (devpor == 'b0)
begin
if (ipower_up == 0) // "low"
iregout <= 'b0;
else if (ipower_up == 1) // "high"
iregout <= 'b1;
end
else if (devclrn == 'b0)
iregout <= 'b0;
else if (iaclr === 'b1)
iregout <= 'b0 ;
else if (iaload === 'b1)
iregout <= idatac;
else if (iena === 'b1 && clk_in === 'b1 &&
clk_last_value === 'b0)
begin
if (isynch_mode == 1)
begin
if (isclr === 'b1)
iregout <= 'b0 ;
else if (isload === 'b1)
iregout <= idatac;
else if (icascade_mode == 1)
iregout <= iregcascin;
else
iregout <= idatain;
end
else if (icascade_mode == 1)
iregout <= iregcascin;
else
iregout <= idatain;
end
end
clk_last_value = clk_in;
end
and (regout, iregout, 1'b1);
and (qfbkout, iregout, 1'b1);
endmodule
///////////////////////////////////////////////////////////////////////
//
// Module Name : maxii_lcell
//
// Description : Verilog simulation model for MAXII Lcell, including
// the following sub module(s):
// 1. maxii_asynch_lcell
// 2. maxii_lcell_register
//
///////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
module maxii_lcell (
clk,
dataa,
datab,
datac,
datad,
aclr,
aload,
sclr,
sload,
ena,
cin,
cin0,
cin1,
inverta,
regcascin,
devclrn,
devpor,
combout,
regout,
cout,
cout0,
cout1
);
parameter operation_mode = "normal" ;
parameter synch_mode = "off";
parameter register_cascade_mode = "off";
parameter sum_lutc_input = "datac";
parameter lut_mask = "ffff" ;
parameter power_up = "low";
parameter cin_used = "false";
parameter cin0_used = "false";
parameter cin1_used = "false";
parameter output_mode = "reg_and_comb";
parameter lpm_type = "maxii_lcell";
parameter x_on_violation = "on";
// INPUT PORTS
input dataa;
input datab;
input datac;
input datad;
input clk;
input aclr;
input aload;
input sclr;
input sload;
input ena;
input cin;
input cin0;
input cin1;
input inverta;
input regcascin;
input devclrn;
input devpor ;
// OUTPUT PORTS
output combout;
output regout;
output cout;
output cout0;
output cout1;
tri1 devclrn;
tri1 devpor;
// INTERNAL VARIABLES
wire dffin, qfbkin;
maxii_asynch_lcell lecomb (
.dataa(dataa),
.datab(datab),
.datac(datac),
.datad(datad),
.cin(cin),
.cin0(cin0),
.cin1(cin1),
.inverta(inverta),
.qfbkin(qfbkin),
.regin(dffin),
.combout(combout),
.cout(cout),
.cout0(cout0),
.cout1(cout1)
);
defparam lecomb.operation_mode = operation_mode;
defparam lecomb.sum_lutc_input = sum_lutc_input;
defparam lecomb.cin_used = cin_used;
defparam lecomb.cin0_used = cin0_used;
defparam lecomb.cin1_used = cin1_used;
defparam lecomb.lut_mask = lut_mask;
maxii_lcell_register lereg (
.clk(clk),
.aclr(aclr),
.aload(aload),
.sclr(sclr),
.sload(sload),
.ena(ena),
.datain(dffin),
.datac(datac),
.regcascin(regcascin),
.devclrn(devclrn),
.devpor(devpor),
.regout(regout),
.qfbkout(qfbkin)
);
defparam lereg.synch_mode = synch_mode;
defparam lereg.register_cascade_mode = register_cascade_mode;
defparam lereg.power_up = power_up;
defparam lereg.x_on_violation = x_on_violation;
endmodule
///////////////////////////////////////////////////////////////////////////////
//
// MAXII UFM ATOM
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps/1 ps
// MODULE DECLARATION
module maxii_ufm (program, erase, oscena, arclk, arshft, ardin, drclk,
drshft, drdin, sbdin, devclrn, devpor, ctrl_bgpbusy, busy,
osc, drdout, sbdout, bgpbusy);
// PARAMETER DECLARATION
parameter address_width = 9;
parameter init_file = "none";
parameter lpm_type = "maxii_ufm";
parameter mem1 = {512{1'b1}};
parameter mem2 = {512{1'b1}};
parameter mem3 = {512{1'b1}};
parameter mem4 = {512{1'b1}};
parameter mem5 = {512{1'b1}};
parameter mem6 = {512{1'b1}};
parameter mem7 = {512{1'b1}};
parameter mem8 = {512{1'b1}};
parameter mem9 = {512{1'b1}};
parameter mem10 = {512{1'b1}};
parameter mem11 = {512{1'b1}};
parameter mem12 = {512{1'b1}};
parameter mem13 = {512{1'b1}};
parameter mem14 = {512{1'b1}};
parameter mem15 = {512{1'b1}};
parameter mem16 = {512{1'b1}};
parameter osc_sim_setting = 180000; // default osc frequency to 5.56MHz
parameter program_time = 1600000; // default program time is 1600ns
parameter erase_time = 500000000; // default erase time is 500us
//constant
parameter widthdata = 16; // fixed data width of 16
parameter widthadd = 9; // fixed address width of 9
parameter sector0_range = 1<<(address_width-1);
// Timing delay pulse
parameter TOSCMN_PW = (osc_sim_setting != 0 ) ? (osc_sim_setting / 2) : 90000; // Pulse width of Minimum Oscillator
// Frequency
parameter TPPMX = (program_time != 0) ? program_time : 1600000; // Maximum Length of Busy Pulse During a
// Program, default is 1600ns
parameter TEPMX = (erase_time != 0) ? (erase_time/1000) : 500000000; // Maximum Length of Busy Pulse During an
// Erase, default is 500 ms; current
// constant is 500 us; need to multiply
// 1000 to get correct value of 500 ms.
// INPUT PORT DECLARATION
input program;
input erase;
input oscena;
input arclk;
input arshft;
input ardin;
input drclk;
input drshft;
input drdin;
input sbdin;
input devclrn; // simulation only port; simulate device-level clear
input devpor; // simulation only port; simulate power-up-reset
input ctrl_bgpbusy; // simulation only port; used to control and emulate
// the output behaviour of bgpbusy
// OUTPUT PORT DECLARATION
output busy;
output osc;
output drdout;
output sbdout;
output bgpbusy;
// INTERNAL SIGNAL/REGISTER DECLARATION
// for memory initialization
reg [(widthdata * (1 << (widthadd - 1)) - 1):0] ufm_initf_sec0;
reg [(widthdata * (1 << (widthadd - 1)) - 1):0] ufm_initf_sec1;
reg [(widthdata-1):0] init_word0; // current init word for sector0
reg [(widthdata-1):0] init_word1; // current init word for sector1
// for simulation
reg [(widthdata-1):0] ufm_storage [0:(1<<address_width)-1]; // ufm sector0
// and sector1
reg [address_width-1:0] addr_reg; // internal address register
reg [address_width-1:0] address_now; // Latest address value
reg [(widthdata-1):0] data_reg; // internal data register
reg [(widthdata-1):0] data_now; // Latest data value in register
reg [(widthdata-1):0] storage_output; // data output from user flash storage
reg osc_str; // store the value of the oscillator
reg program_pulse; // indicate program cycle is running
reg erase_pulse; // indicate erase cycle is running
reg first_warning; // warn the user once about oscillator range
reg program_reg; // program signal must be registered by rising osc edge
reg erase_reg; // erase signal must be registered by rising osc edge
// INTERNAL WIRE DECLARATION
wire [address_width-1:0] address_tmp;
wire [(widthdata-1):0] new_read_data;
wire [(widthdata-1):0] data_tmp;
wire sys_busy;
wire gated_arclk;
wire gated_drclk;
wire data_reg_msb;
wire int_osc; // internal oscillator
// INTERNAL TRI DECLARATION
tri0 erase;
tri0 program;
tri0 ctrl_bgpbusy;
tri0 sbdin;
tri0 drdin;
// Buffer Declaration
wire i_program;
wire i_erase;
wire i_oscena;
wire i_arclk;
wire i_arshft;
wire i_ardin;
wire i_drclk;
wire i_drshft;
wire i_drdin;
wire i_sbdin;
buf (i_program, program);
buf (i_erase, erase);
buf (i_oscena, oscena);
buf (i_arclk, arclk);
buf (i_arshft, arshft);
buf (i_ardin, ardin);
buf (i_drclk, drclk);
buf (i_drshft, drshft);
buf (i_drdin, drdin);
buf (i_sbdin, sbdin);
// LOCAL INTEGER DECLARATION
integer i, j, k, l, n; // looping index
integer mem_cnt, bit_cnt; // looping index
integer numwords; // number of UFM words
// DELAY SPECIFICATION
specify
(sbdin => sbdout) = (0, 0);
$setup (arshft, posedge arclk, 0);
$setup (ardin, posedge arclk, 0);
$setup (drshft, posedge drclk, 0);
$setup (drdin, posedge drclk, 0);
$setup (oscena, posedge program, 0);
$setup (oscena, posedge erase, 0);
$hold (posedge arclk, arshft, 0);
$hold (posedge arclk, ardin, 0);
$hold (posedge drclk, drshft, 0);
$hold (posedge drclk, drdin, 0);
$hold (posedge drclk, program, 0);
$hold (posedge arclk, erase, 0);
$hold (negedge busy, program, 0);
$hold (negedge busy, erase, 0);
$hold (negedge program, oscena, 0);
$hold (negedge erase, oscena, 0);
(posedge program => (busy +: 1'b1)) = (0, 0) ;
(posedge erase => (busy +: 1'b1)) = (0, 0) ;
(posedge drclk => (drdout +: data_reg_msb)) = 0;
(posedge oscena => (osc +: 1'b1)) = (0, 0);
endspecify
// INITIAL CONSTRUCT BLOCK
initial
begin
`ifdef QUARTUS_MEMORY_PLI
$memory_connect(ufm_storage);
`endif
first_warning <= 1;
// Check for invalid parameters
if (address_width != widthadd)
begin
$display("Error! address_width parameter must be equal to %d.", widthadd);
end
if (widthdata != 16)
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