?? xil_rgb2ycrcb_config.m
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function Xil_RGB2YCrCb_config(this_block)
% Revision History:
%
% 18-Sep-2005 (23:07 hours):
% Original code was machine generated by Xilinx's System Generator after parsing
% D:\VideoBlockset\development\HDL_src\ColorSpace\testbench\Xil_colorspaceRGB2YCrCb.vhd
%
%
mybb = this_block.blockName;
color_sub = get_param(mybb,'Parent');
param_a = str2num(get_param(color_sub, 'coefA'));
param_b = str2num(get_param(color_sub, 'coefB'));
param_d = str2num(get_param(color_sub, 'coefC'));
param_c = str2num(get_param(color_sub, 'coefD'));
ymax = str2num(get_param(color_sub, 'ymax'));
ymin = str2num(get_param(color_sub, 'ymin'));
clip = strcmp(get_param(color_sub, 'has_clip'),'on');
clamp = strcmp(get_param(color_sub, 'has_clamp'),'on');
yoffset = str2num(get_param(color_sub, 'yoffset'));
coffset = str2num(get_param(color_sub, 'coffset'));
cmax = str2num(get_param(color_sub, 'cmax'));
cmin = str2num(get_param(color_sub, 'cmin'));
in_bits = str2num(get_param(color_sub, 'in_bits'));
out_bits= str2num(get_param(color_sub, 'out_bits'));
c_bits = str2num(get_param(color_sub, 'c_bits'));
m_bits = str2num(get_param(color_sub, 'm_bits'));
fabric_adds = double(strcmp(get_param(color_sub, 'fabric_adds'),'on'));
v4 = double(strcmp(lower(this_block.getDeviceFamilyName()), 'virtex4'));
this_block.setTopLevelLanguage('VHDL');
this_block.setEntityName('Xil_RGB2YCrCb_sg');
% System Generator has to assume that your entity has a combinational feed through;
% if it doesn't, then comment out the following line:
this_block.tagAsCombinational;
this_block.addSimulinkInport('R');
this_block.addSimulinkInport('G');
this_block.addSimulinkInport('B');
this_block.addSimulinkInport('V_SYNC_in');
this_block.addSimulinkInport('H_SYNC_in');
this_block.addSimulinkInport('PIX_EN_in');
this_block.addSimulinkInport('en');
this_block.addSimulinkInport('rst');
this_block.addSimulinkOutport('Y');
this_block.addSimulinkOutport('Cr');
this_block.addSimulinkOutport('Cb');
this_block.addSimulinkOutport('V_SYNC_out');
this_block.addSimulinkOutport('H_SYNC_out');
this_block.addSimulinkOutport('PIX_EN_out');
vsyncout_port = this_block.port('V_SYNC_out');
vsyncout_port.setType('UFix_1_0');
vsyncout_port.useHDLVector(false);
hsyncout_port = this_block.port('H_SYNC_out');
hsyncout_port.setType('UFix_1_0');
hsyncout_port.useHDLVector(false);
pixenout_port = this_block.port('PIX_EN_out');
pixenout_port.setType('UFix_1_0');
pixenout_port.useHDLVector(false);
if (this_block.inputTypesKnown)
v4 = double(strcmp(lower(this_block.getDeviceFamilyName()), 'virtex4'));
% do input type checking, dynamic output type and generic setup in this code block.
if (this_block.port('V_SYNC_in').width ~= 1)
this_block.setError('Input data type for port "V_SYNC_in" must have width=1');
end
this_block.port('V_SYNC_in').useHDLVector(false);
if (this_block.port('H_SYNC_in').width ~= 1)
this_block.setError('Input data type for port "H_SYNC_in" must have width=1');
end
this_block.port('H_SYNC_in').useHDLVector(false);
if (this_block.port('PIX_EN_in').width ~= 1)
this_block.setError('Input data type for port "PIX_EN_in" must have width=1');
end
this_block.port('PIX_EN_in').useHDLVector(false);
if (this_block.port('en').width ~= 1)
this_block.setError('Input data type for port "en" must have width=1');
end
this_block.port('en').useHDLVector(false);
if (this_block.port('rst').width ~= 1)
this_block.setError('Input data type for port "rst" must have width=1');
end
this_block.port('rst').useHDLVector(false);
if (this_block.port('R').width ~= in_bits) error('Width of port R not equal with input bits specified through GUI'); end
if (this_block.port('G').width ~= in_bits) error('Width of port G not equal with input bits specified through GUI'); end
if (this_block.port('B').width ~= in_bits) error('Width of port B not equal with input bits specified through GUI'); end
this_block.port('Y').width = out_bits;
this_block.port('Cr').width = out_bits;
this_block.port('Cb').width = out_bits;
this_block.port('V_SYNC_out').width = 1;
this_block.port('H_SYNC_out').width = 1;
this_block.port('PIX_EN_out').width = 1;
this_block.addGeneric('family_has_mac', v4);
this_block.addGeneric('fabric_adds', fabric_adds);
this_block.addGeneric('iwidth', in_bits);
this_block.addGeneric('cwidth', c_bits );
this_block.addGeneric('mwidth', m_bits );
this_block.addGeneric('owidth', out_bits);
this_block.addGeneric('acoef', round(param_a*pow2(c_bits-1)));
this_block.addGeneric('bcoef', round(param_b*pow2(c_bits-1)));
this_block.addGeneric('ccoef', round(param_c*pow2(c_bits-1)));
this_block.addGeneric('dcoef', round(param_d*pow2(c_bits-1)));
this_block.addGeneric('has_clip', 'integer', num2str(clip));
this_block.addGeneric('has_clamp', 'integer', num2str(clamp));
this_block.addGeneric('ymax', ymax);
this_block.addGeneric('ymin', ymin);
this_block.addGeneric('cmax', cmax);
this_block.addGeneric('cmin', cmin);
this_block.addGeneric('yoffset', yoffset);
this_block.addGeneric('coffset', coffset);
end % if(inputTypesKnown)
if (this_block.inputRatesKnown)
setup_as_single_rate(this_block,'clk','ce')
end % if(inputRatesKnown)
this_block.addFile('../GenXlib_utils.vhd');
this_block.addFile('../GenXlib_arch.vhd');
this_block.addFile('../color_space_pkg.vhd');
this_block.addFile('../Xil_RGB2YCrCb.vhd');
this_block.addFile('Xil_RGB2YCrCb_sg_wrap.vhd');
return;
% ------------------------------------------------------------
function setup_as_single_rate(block,clkname,cename)
inputRates = block.inputRates;
uniqueInputRates = unique(inputRates);
if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf)
block.setError('The inputs to this block cannot all be constant.');
return;
end
if (uniqueInputRates(end) == Inf)
hasConstantInput = true;
uniqueInputRates = uniqueInputRates(1:end-1);
end
if (length(uniqueInputRates) ~= 1)
block.setError('The inputs to this block must run at a single rate.');
return;
end
theInputRate = uniqueInputRates(1);
for i = 1:block.numSimulinkOutports
block.outport(i).setRate(theInputRate);
end
block.addClkCEPair(clkname,cename,theInputRate);
return;
% ------------------------------------------------------------
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