--SINGLE_FILE_TAG--------------------------------------------------------------------------------- $Id: pvr.vhd,v 1.3 2007/12/13 13:56:42 stefana Exp $--------------------------------------------------------------------------------- pvr.vhd - entity/architecture pair----------------------------------------------------------------------------------- ****************************************************************************-- ** Copyright(C) 2001-2005 by Xilinx, Inc. All rights reserved.-- **-- ** This text contains proprietary, confidential information of-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,-- ** and may be used, copied and/or disclosed only pursuant to the-- ** terms of a valid license agreement with Xilinx, Inc. -- **-- ** Unmodified source code is guaranteed to place and route, -- ** function and run at speed according to the datasheet-- ** specification. Source code is provided "as-is", with no-- ** obligation on the part of Xilinx to provide support.-- **-- ** Xilinx Hotline support of source code IP shall only include-- ** standard level Xilinx Hotline support, and will only address-- ** issues and questions related to the standard released Netlist-- ** version of the core (and thus indirectly, the original core source-- **-- ** The Xilinx Support Hotline does not have access to source-- ** code and therefore cannot answer specific questions related-- ** to source HDL. The Xilinx Support Hotline will only be able-- ** to confirm the problem in the Netlist version of the core.-- **-- ** This copyright and support notice must be retained as part-- ** of this text at all times.-- ****************************************************************************----------------------------------------------------------------------------------- Filename: pvr.vhd-- Description: Read select of Processor Version Register array---- VHDL-Standard: VHDL'93--------------------------------------------------------------------------------- Structure:   --              pvr.vhd----------------------------------------------------------------------------------- Author:          roland-- History:--   roland  2005-12-01    - First Version----------------------------------------------------------------------------------- Naming Conventions:--      active low signals:                     "*_n"--      clock signals:                          "clk", "*_clk"--      reset signals:                          "rst", "*_rst", "reset"--      generics:                               All uppercase, starting with: "C_"--      constants:                              All uppercase, not starting with: "C_"--      state machine next state:               "*_next_state"--      state machine current state:            "*_curr_state"--      pipelined signals:                      "*_d#"--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"--      internal version of output port:        "*_i"--      ports:                                  Names begin with uppercase--      component instantiations:               "<ENTITY_>I_<#|FUNC>" , "ENTITY>_I#" ---- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that-- stage:----    IF                      -- instruction fetch--    OF                      -- operand fetch--    EX                      -- execute--    MEM                     -- memory--    WB                      -- write back-------------------------------------------------------------------------------library IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;---------------------------------------------------------------------------- Include MicroBlaze package for data types--------------------------------------------------------------------------library Microblaze_v7_10_a;use Microblaze_v7_10_a.MicroBlaze_ISA.all;use Microblaze_v7_10_a.MicroBlaze_Types.all;library unisim;use unisim.vcomponents.all;--------------------------------------------------------------------------------- Port Declaration-------------------------------------------------------------------------------entity PVR is  generic (    -- PVR0 Basic    C_PVR                   : integer;   -- Which PVR mode None=0, Basic=1, Full=2    C_MB_VERSION            : std_logic_vector(0 to 7);    C_PVR_USER1             : std_logic_vector(0 to 7);    -- PVR1 User defined    C_PVR_USER2             : std_logic_vector(0 to 31);    -- PVR2 Configuration    C_D_OPB                 : integer;    C_D_LMB                 : integer;    C_I_OPB                 : integer;    C_I_LMB                 : integer;    C_INTERRUPT_IS_EDGE     : integer;    C_EDGE_IS_POSITIVE      : integer;    C_D_PLB                 : integer;    C_I_PLB                 : integer;    C_INTERCONNECT          : integer;    C_USE_MSR_INSTR         : boolean;    C_USE_PCMP_INSTR        : boolean;    C_AREA_OPTIMIZED        : boolean;    C_USE_BARREL            : boolean;    C_USE_DIV               : boolean;    C_USE_HW_MUL            : boolean;    C_USE_FPU               : integer;    C_USE_MUL64             : boolean;    C_IPLB_BUS_EXCEPTION    : integer;    C_DPLB_BUS_EXCEPTION    : integer;    C_OPCODE_0x0_ILLEGAL    : integer;    C_UNALIGNED_EXCEPTIONS  : integer;    C_ILL_OPCODE_EXCEPTION  : integer;    C_IOPB_BUS_EXCEPTION    : integer;    C_DOPB_BUS_EXCEPTION    : integer;    C_DIV_ZERO_EXCEPTION    : integer;    C_FPU_EXCEPTION         : integer;    C_FSL_EXCEPTION         : integer;    C_USE_EXTENDED_FSL_INSTR  : integer;    -- PVR3 Debug and FSL    C_DEBUG_ENABLED         : integer;    C_NUMBER_OF_PC_BRK      : integer;    C_NUMBER_OF_RD_ADDR_BRK : integer;    C_NUMBER_OF_WR_ADDR_BRK : integer;    C_FSL_LINKS             : integer;    -- PVR4 Instruction Cache    C_USE_ICACHE            : integer;    C_ADDR_TAG_BITS         : integer;    C_ICACHE_USE_FSL        : integer;    C_ALLOW_ICACHE_WR       : integer;    C_ICACHE_LINE_LEN       : integer;    C_CACHE_BYTE_SIZE       : integer;    C_ICACHE_ALWAYS_USED    : integer;    -- PVR5 Data Cache     C_USE_DCACHE            : integer;    C_DCACHE_ADDR_TAG       : integer;    C_DCACHE_USE_FSL        : integer;    C_ALLOW_DCACHE_WR       : integer;    C_DCACHE_LINE_LEN       : integer;    C_DCACHE_BYTE_SIZE      : integer;    C_DCACHE_ALWAYS_USED    : integer;    -- PVR6 Instruction Cache Base Address    C_ICACHE_BASEADDR       : std_logic_vector(0 to 31);    -- PVR7 Instruction Cache High Address    C_ICACHE_HIGHADDR       : std_logic_vector(0 to 31);    -- PVR8 Data Cache Base Address    C_DCACHE_BASEADDR       : std_logic_vector(0 to 31);    -- PVR9 Data Cache High Address    C_DCACHE_HIGHADDR       : std_logic_vector(0 to 31);    -- PVR10 Target    C_TARGET                : TARGET_FAMILY_TYPE;    -- PVR11 MMU and reset value for MSR register    C_USE_MMU               : integer;    C_MMU_DTLB_SIZE         : integer;    C_MMU_ITLB_SIZE         : integer;    C_MMU_TLB_ACCESS        : integer;    C_MMU_ZONES             : integer;    C_RESET_MSR             : std_logic_vector(MSR_REG_POS_TYPE)    );  port (    -- Common signals.    Clk             : in  std_logic;    Reset           : in  std_logic;        -- PVR read interface.    MEM_PipeRun     : in  boolean;                   -- Move the memory stage    MEM_PVR_Select  : in  std_logic_vector(0 to 3);  -- Select which PVR to read    MEM_Sel_SPR_PVR : in  boolean;                   -- Select SPR processor version register    WB_Sel_SPR_PVR  : in  boolean;                   -- Select SPR processor version register    WB_PVR          : out PVR_TYPE                   -- PVR Read port     );  end entity PVR;---------------------------------------------------------------------------- Architecture section--------------------------------------------------------------------------architecture IMP of PVR is  -- Most significant PVR defined   constant PVR_HIGH : natural := 15;   type PVR_Array_Type is array (0 to PVR_HIGH) of PVR_TYPE;  -- Full PVR array  -- Convert integer binary chaice to std_logic  function int2std (val : integer) return std_logic is  begin  -- function int2std    if (val = 0) then      return '0';    else