------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date:    11:13:07 04/17/2009 -- Design Name: -- Module Name:    SANJIAOBO - RTL -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity SANJIAOBO is    Port ( CLK : in  STD_LOGIC;           RESET : in  STD_LOGIC;			  PUT_HZ:in STD_LOGIC_VECTOR(7 downto 0);           SANJIAO_DATA : out  STD_LOGIC_VECTOR(7 downto 0));end SANJIAOBO;architecture RTL of SANJIAOBO issignal TEMP :STD_LOGIC_VECTOR(7 downto 0);signal UPDN: STD_LOGIC;signal UNIT_HZ:integer range 0 to 1000000;signal SIN_CLK:STD_LOGIC;signal count_hz:integer range 0 to 100000;signal cha:integer range 0 to 1000000;signal PUT_HZ_integer:integer range 0 to 255;beginPUT_HZ_integer<=240;--根據輸入的頻率算出脈沖個數；process(CLK,PUT_HZ_integer)beginif rising_edge(CLK) then case (PUT_HZ_integer) isWHEN 0 to 40  =>  UNIT_HZ <= 1943;   --頻率為0-10HZ時，載波比為201；WHEN 41 to 80 =>  UNIT_HZ  <= 2657;  --頻率為10.25-20HZ時，載波比為147；WHEN 81 to 120 => UNIT_HZ <= 3946;  --頻率為20.25-30HZ?保?載波比為99；WHEN 121 to 160 => UNIT_HZ <= 5661; --頻率為30.25-40HZ時，載波???9；WHEN 161 to 200 => UNIT_HZ <= 8681; --頻率40.25-50HZ時，載波比為45；WHEN 201 to 240 => UNIT_HZ <= 11837;  --頻率為50.25-60HZ時，載波比為33；WHEN others     => UNIT_HZ <= 11837;end case;end if;end process;process(PUT_HZ_integer,CLK,RESET)beginif RESET='0' thencount_hz<=1;cha<=UNIT_HZ;elsif rising_edge(CLK) then    if(cha>=PUT_HZ_integer) then	  cha<=UNIT_HZ-count_hz*PUT_HZ_integer;	  count_hz<=count_hz+1;	  SIN_CLK<='0';	else	 count_hz<=1;	 cha<=UNIT_HZ;	 SIN_CLK<='1';	 end if;end if;end process;process(SIN_CLK,RESET)beginif RESET='0'then   TEMP <="00000000";	UPDN<='1';elsif rising_edge(SIN_CLK) then     if (UPDN='1')  then				    TEMP <=TEMP + 1;
		 if TEMP="11111110" then       UPDN<= not UPDN ;
		 end if;    elsif (UPDN='0') then       TEMP <= TEMP - 1;
		 if TEMP="00000001" then       UPDN<='1';    end if;	 		 end if;   end if;end process;SANJIAO_DATA <=TEMP;end RTL;